Film to video format converter using least significant look-up table

ABSTRACT

A format converter is provided for converting without loss of picture information a motion picture film image to and/or from a given recorder/player format. The recorder/player stores chrominance and luminance data as 8 bit digital samples. The motion picture chrominance information is also provided as 8 bit samples. The motion picture luminance data is provided either 9 or 10 bit samples. The 8 most significant bits of each luminance sample are stored as sequential 8 bit samples in the fields of the player/recorder. The additional 1 or 2 bits per luminance sample is/are stored at the end of the sequential 8 bit samples in each field of the recorder/player. During replay, the additional 1 or 2 bits per sample is/are matched with a corresponding 8 bit sample to reform 9 or 10 bit luminance samples.

REFERENCE TO THE PARENT APPLICATIONS

This application is a continuation-in-part of application Ser. No.08/057,495, (now U.S. Pat. No. 5,617,218), filed May 6, 1993, which is acontinuation-in-part of application Ser. No. 07/404,190 (now U.S. Pat.No. 5,280,397), filed Sep. 7, 1989. This application is also acontinuation-in-part of application Ser. No. 08/053,230(now U.S. Pat.No. 5,504,532), filed Apr. 28, 1993, which is also acontinuation-in-part of application Ser. No. 07/404,190 (now U.S. Pat.No. 5,280,397), filed Sep. 7, 1989.

BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates to high definition television and motion picturefilm images and, more particularly, relates to a method and apparatusfor converting without loss of picture information a high definitiontelevision format to and from a given recorder/player format, and amotion picture film image format to and from a given recorder/playerformat.

2. Related Information

Prior to the introduction in the United States and Japan of the existingNTSC standard television signal format and the introduction in Europe ofthe PAL and SECAM formats, there was considerable discussion over whichbroadcast black and white format to choose. Some broadcast formats weredesirable because they exhibited less RF interference when transmitted.Other broadcast formats were desirable because they delivered atelevision picture having a sharper or less choppy image. Discussionagain occurred, upon the introduction of color television, over whichcolor signal broadcast format to choose and whether the chosen colorformat should be compatible with the broadcast black and whitetelevision format. In the United States today, the same issues are againbeing raised over the choice of a second generation televisionformat--commonly known as high definition television (HDTV) or advancedtelevision (ATV). Recent issues include discussion concerning whichformat is best suited for conventional over-the-air broadcast as well asbest suited for transmission over new mediums such as fiber optic cable,coaxial cable, telephonic, broadcast satellite, and pre-recordedmediums. The recent issues include discussion of whether the new HDTVformat should be compatible with the present NTSC format. While theFederal Communications Commission of the United States would like thenew format to be NTSC compatible, there is considerable influenceworld-wide to adopt a totally new standard. The discussion furtherincludes the issue of whether a proposed format will be adverselyaffected during broadcast or transmission on the new mediums and whethersuch a proposed format will subjectively provide an adequate picture.Many formats have been proposed for adoption by proponents both insideand outside the United States.

The Advanced Television Test Center was established in Alexandria, Va.,as a neutral test center for evaluation and comparison of proposed HDTVformats. Besides testing the proposed HDTV formats for immunity toelectrical interference and other impairments and testing for NTSCcompatibility, the proposed HDTV formats are shown to viewers forsubjective evaluation. Viewers compare, by psycho-physical testing, theproposed HDTV formats and rate them as to their characteristics with andwithout transmission impairments. In order to perform testing on allproposed formats, the television test center has a need for a uniformvideo tape recorder which can record all proposed source formats.

Such a uniform video source may be provided by a video tape recordercapable of recording any one of all proposed HDTV formats and playingback in the recorded HDTV format. Several digital video tape recorders(DVTR), for example, the Sony HDD-1000 and the Hitachi DVTR, are capableof recording or playing back a HDTV signal. Either the Sony or theHitachi video tape recorder is capable of recording 1920 bytes ofluminance data at 74.25 megabytes per second and two chrominance datacomponents comprising another 1920 bytes per line at 74.25 megabytes persecond as packets of data. Digital data packets are recorded at a rateof 1035 lines per frame with each frame having 2 fields. The HDD-1000has a field rate of 60 Hz at which 74.25 megabytes per second arerecorded as mentioned above. The HDD-1000 can also be used at a fieldrate of 59.94 Hz at which 74.175 megabytes per second as recorded. Thefield rate of 59.94 Hz is actually 60×(1000/1001) Hz. While a DVTR iscapable of recording and playing back in accordance with theabove-described input/output specifications, a requirement remains toprovide an interface for such a recorder allowing other source formatsto be recorded uniformly without the introduction of losses.

Prior systems have been proposed for recording at least one format on asingle video tape recorder. For example, U.S. Pat. No. 4,549,224, issuedto Nakamura et al., provides an apparatus for recognizing either an NTSCor a PAL/SECAM format and generating an appropriate recording frequencydependent on the recognized format. The Nakamura system is incapable ofrecording proposed high definition television formats. Furthermore, theNakamura system does not perform signal conversion for recording orplayback in a desired format.

Systems are also known for providing conversion between televisionformats. Many systems, however, are incapable of converting televisionformats without loss or alteration of picture quality. At the AdvancedTelevision Test Center, conversion between formats must occur withoutalteration of picture quality or loss of information content. All knownconversion systems use interpolation techniques and approximationalgorithms for this type of conversion. For instance, U.S. Pat. No.4,587,556, issued to Collins, discloses a television standard converterfor converting conventional PAL and NTSC signals using weighing factorsand interpolation. Furthermore, U.S. Pat. No. 4,276,565, issued toDalton et al., converts conventional television formats usinginterpolation. U.S. Pat. No. 4,658,284, issued to Kawamura et al., iscapable of downsizing a 625 line PAL format to a 525 line format forprinting on a color printer. Interpolation is used for downsizingconversion. Conversion between conventional formats is also performed inU.S. Pat. No. 4,661,862 issued to Thompson, wherein data reduction isperformed by deletion and in U.S. Pat. No. 4,283,736, issued to Morio etal., wherein conversion by discarding or repeating information signalsis performed. Such schemes entail loss in picture quality or content.Interpolation itself is a filtering function. Some information must belost and therefore such schemes cannot be truly bi-directional.

Other systems such as that disclosed in U.S. Pat. No. 4,743,958, issuedto Bannister et al. convert conventional encoded NTSC, PAL, SECAM andanalog RGB, YUV to separate chrominance and luminance signals for inputto a special effects device. Bannister et al. performs the conversionusing filters for processing the signals. U.S. Pat. No. 4,463,387,issued to Hashimoto et al., processes video data both before recordingand after playback for quality improvement. No conversion is performed.

Systems for adapting an input to, a VCR include U.S. Pat. No. 4,597,020,issued to Wilkinson, wherein a video signal is shuffled before recordingand unshuffled upon playback to disburse bursts of errors. U.S. Pat. No.4,530,048, issued to Proper, adapts a VCR for computer memory backupstorage. Proper concerns interfacing a VCR to avoid VCR informationdropouts, a problem of no concern for digital video recording. U.S. Pat.No. 4,638,380, issued to Wilkinson et al., discloses a multiple headvideo tape recorder with switching and interpolation to remove theeffects of a failed head.

Yet another system disclosed in U.S. Pat. No. 4,797,746 to Ashcraft isdirected to a system for converting digital image information in astorage format to a format such as a digital scan converter or standardtelevision format. The disclosed system includes a high bit rateinterface unit (HBRI) comprising an input controller, an image bufferRAM, an output controller and a system controller. The HBRI receivesstored data from a storage device, such as a tape unit or an opticaldisk, and based on commands output from the system controller, convertsthe received data to another format. The system controller commands theinput controller as to the location in the image buffer RAM where eachdata point or bit is read. The output controller is responsive to thecommands of the system controller for reading out each data point fromthe image buffer RAM so that a standard digital scan converter format ortelevision format is produced.

U.S. Pat. No. 4,577,240 to Hedberg et al. relates to a system capable ofon-line acquisition, processing and display of radiographs and foroff-line recording, retrieval, review, image processing and archivalstorage of images. The disclosed system includes word formatter circuitswhich convert incoming digital data having a width of between 6 and 10bits into a sequence of 5 separate data streams for recording into acentralized library. The word formatter circuits are used in playback toconvert the recorded data for display by HDTV direct imaging orfluoroscopy to produce film quality images.

U.S. Pat. No. 4,651,208 was issued to Charles Rhodes, the inventor ofthe present application, and was assigned to an assignee other than theassignee of the present application. The patent discloses conversionbetween widescreen and non-widescreen television transmissions usinginput/output multiplexers for line conversion in line memory pairs.Picture lines are clocked into and out of a memory to change the aspectration of a picture from a large to a small picture aspect ratio. Theprocess is not bi-directional because side panel pixels are discardedwhen a wide aspect ratio image such as 16:9, is converted to a less wideaspect ratio image, such as 4:3. Afterwards, the reduced aspect ratioimage cannot be reconverted back to the original wide aspect ratioimage.

None of the above systems provide a uniform video source for equallycomparing proposed high definition television formats. Knowninterpolators and filters unfortunately reproduce and convert highdefinition television signals with the sacrifice of picture information.While the invention disclosed in aforementioned U.S. Pat. No. 4,651,208to Rhodes relates to a method and apparatus for converting widescreentelevision signals for display on non-widescreen television displays,the process is irrevocable and does not facilitate video recording.

There also exists in the motion picture industry a need to achievemotion picture film. The motion picture film used to record motionpictures is very fragile. It decays with age, and each showing of thefilm additionally wears the film. For many motion picture studios, oneof their major assets is their film library. The remains today a demandfor classic motion pictures filmed many years ago. There is a need topreserve these motion pictures. However, any achieving method selectedmust store the entire motion picture, without cutting off the edges,etc. Otherwise, the achieving method will not be acceptable to themotion film industry and/or motion picture producers. Also, since eachtime the film is played, it experiences wear, it is preferable that theachieved method provide an achieved copy from which additional mastersmay be made without degradation of the picture quality.

SUMMARY OF THE INVENTION

An important object of the present invention is to provide a recorderfor recording a television format without loss of picture information.

Another object of the present invention is to provide a player forplaying a television format without loss of picture information.

Another object of the present invention is to provide a recorder/playerfor playing back a television format without loss of pictureinformation.

Another object of the present invention is to provide a converter forconverting a television format to digital luminance and chrominance datasignals for recording on a digital video recorder without loss ofpicture information.

Another object of the present invention is to provide a conversioncircuit for playback of digital luminance and chrominance signals in adesired television format without loss of picture information.

A further object of the present invention is to provide a converter forallowing a commercially available digital video tape recorder to recordand playback a television format.

Another object of the present invention is to provide a converter forstoring data from a motion picture film image format in a memory insynchronism with the frame rate of the film image format and reading thedata from the memory in synchronism with the field rate of a targetformat.

Another object of the present invention is to provide a converter whichincludes a plurality of spare lines of data with lines of data from amemory to generate a complete field of a television signal format.

The present invention solves the above-mentioned problems by providing aconverter for converting without loss of picture information any highdefinition television format to and from a given recorder/player format.The format converter of the present invention provides an interface forconverting between RGB and luminance/chrominance inputs and betweenanalog and digital inputs. The interface couples any proposed highdefinition television format to a plurality of memory pairs. A clock andcontrol circuit controls addressing of the memories for reading andwriting so that conversion is performed between any high definitiontelevision format and the format required for the Sony HDD-1000 orHitachi digital video tape recorder or any other comparable recorder.

In particular, during a record mode of operation, involving both aconverter according to the present invention and a digital video taperecorder, the converter is responsive to horizontal and vertical drivesynchronizing signals provided by a source format. The source formatsignal is digitized and stored in a memory at one rate and read from thememory at the rate of operation of the DVTR. An advantage of the presentinvention is that the size of the memory may be simultaneously limitedand the clocking and controlling of the converter memory facilitatedwithout any loss in the proponent's signal regardless of the inputsignal format. Furthermore, the reading of converter memory and writingof data into the DVTR are controlled and synchronized by the controlsignals provided by the source format.

During a playback mode of operation, the converter, according to thepresent invention, becomes the source of controlling the DVTR and theoutput to the broadcaster. Nevertheless, the same limited size memorymay be employed with the same advantage as during the record mode.

In the event one of the proposed HDTV formats other than those formatsbased upon the format for which commercially available recorders aredesigned is adopted by the Federal Communications Commission in theUnited States, broadcasters will be able to employ the present inventionwith presently available commercial DVTRs (such as the Sony HDD-1000 orHitachi DVTR) to record and playback HDTV pictures and audio--not havingto await development of a new HDTV DVTR specifically constructed for theadopted format at an uncertain delay and possibly greater realized cost.

In another embodiment of the invention, a telecine, or similar devices,is used to digitize a successive frames of motion picture. The digitaldata is converted to a format compatible with a known DVTR and stored inthe DVTR. Therefore, a digital copy of the entire motion picture ismade. The digital copy may be stored and perfect copies made at anytime. The digital copy may be read and then converted into an outputformat for viewing by a user, e.g., a television studio.

These and other objects and features of the present invention willbecome evident from the following detailed description of the inventionwhen read in conjunction with the appended drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block schematic diagram of a television test center fortesting and comparing proposed HDTV source formats.

FIG. 2 is a block schematic diagram of components for recording atelevision format on a given digital video recorder.

FIG. 3 is a block schematic diagram of components for playing back asignal on a digital video player in a television format.

FIG. 4 is a detailed block schematic diagram of circuitry for convertingan RGB television signal to digital luminance and chrominance inputs fora given digital tape recorder.

FIG. 5 is a detailed block schematic diagram of components forconverting, to an RGB signal, digital luminance and chrominance outputsfrom a given digital tape player.

FIGS. 6(a) and (b) are record mode and playback mode generic blockschematic diagrams, respectively, for clock and control oscillators.

FIG. 7 illustrates seven lines of a first exemplary source televisionformat included in five lines of a digital luminance signal forrecording on the recorder.

FIG. 8 illustrates seven lines of a first exemplary source televisionformat included in five lines of a digital chrominance signal of therecorder.

FIG. 9 illustrates how samples of lines of fields of a first exemplarysource format are placed in the lines of fields of the digital videorecorder.

FIG. 10 illustrates how samples of the lines of fields of a secondexemplary source format are placed in the lines of fields of the digitaltape recorder.

FIGS. 11(a) and (b) are flowcharts describing the structuring ofconverter parameters for any source format.

FIGS. 12(a) and (b) are record mode and playback mode block schematicdiagrams, respectively, for clock and control oscillators for a firstexemplary source format.

FIG. 13(a) and (b) are record mode and playback mode block schematicdiagrams, respectively, for clock and control oscillators for a secondexemplary source format.

FIGS. 14(a) and (b) are record mode and playback mode block schematicdiagrams, respectively, for a clock and control oscillator for a thirdexemplary source format.

FIG. 15 illustrates how lines of frames of a motion picture film imageare arranged in the lines of fields of a digital video recorder.

FIGS. 16(a) and (b) are record mode and playback mode block schematicdiagrams, respectively, for a clock and control oscillator for motionpicture film image.

FIGS. 17(a) and 17(b) illustrate how lines of frames of a motion picturefilm image are arranged in the lines of fields of a digital videorecorder for enhanced resolution.

FIG. 18 shows a record mode block diagram for recording a motion pictureon a digital video recorder with enhanced resolution.

FIGS. 19(a) and 19(b) show playback mode block diagrams for converting amotion picture stored with enhanced resolution by a digital videorecorder back to a motion picture format.

FIG. 20 illustrate how lines of frames of a motion picture film imageare arranged in the lines of fields of a digital video recorder forenhanced resolution.

FIGS. 21-23 illustrate digital filters for use with the instantinvention to obtain enhanced resolution when recording a motion pictureimage on a digital video recorder.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a television test center utilizing the multiple HDTVformat/recorder players 110 and 150, including converter 160 of thepresent invention. Signal sources for high-definition television areprovided by high-definition digital video tape recorder (DVTR), 110,PIXAR 111 and test signal block 112. Signal sources for test audio areprovided by program audio block 113 and test signal audio block 114.Signal sources for the conventional NTSC format are provided by programsource block 115, video test signal block 116 and audio test signalblock 117. The outputs of the signal sources are directed to test bed120, including RF test bed 121, satellite and microwaves test bed 122and cable test bed 123. At test bed 120, the television signals aresubmiected to impairments including noise conditions, multipath,airplane flutter, two channel signal level and time differentials andinterference. An impaired television signal is then sent from test bed120 to displays 130 for psycho-physical testing by viewers 131. Anactual or impaired signal output from test bed 120 is also sent toprocessing equipment 140 for NTSC compatibility tests. The actual orimpaired signal output from the test bed can be recorded on highdefinition television digital video tape recorder (DVTR) 150.Measurement of the HDTV signal can also be made by spectrum analyzer 141and advanced television audio and visual measurement equipment 142.Digital video tape recorder 150 can also playback directly to highdefinition television displays 130 for psycho-physical testing.

The present invention provides converters 160 used in conjunction withhigh definition digital video tape recorders (DVTR) 110 and 150. DVTR110 plays and DVTR 150 records in only one advanced television format.DVTR 110 is preferably a Sony HDD-1000 or Hitachi digitalrecorder/player having predetermined input/output specificationssubstantially in accordance with Japanese high definition broadcaststandards; however, the principles of the present invention may belikewise applied to other digital signal recorders having otherinput/output specifications. Important specifications for the SonyHDD-1000 are illustrated in Table 1. Important specifications for theHitachi DVTR are illustrated in Table II.

                                      TABLE 1                                     __________________________________________________________________________    PARAMETERS      SPECIFICATIONS                                                __________________________________________________________________________      Coded signals Y, P.sub.B, P.sub.R                                                           These signals are obtained from Gamma Pre-                      or G, B, R    corrected signals                                               Number of samples per total line                                                               Y 2200    G 2200                                             G,B,R or illuminance signal                                                                    P 1100    B 2200                                             Each color difference signal                                                                   P 1100    R 2200                                             (P.sub.B, P.sub.R)                                                            Sampling structure                                                                          Orthogonal Line, Field                                          G,B,R, or illuminance signal                                                                and Frame Repetitive                                            Each color difference signal                                                                The G,S,R sampling structures to be coincident and                            coincident also with the luminance sampling structure                         of the Y, P.sub.B, P.sub.R system. P.sub.B and P.sub.R                        samples cosited                                                               with odd (1st, 3rd, 5th, etc. Y samples in each line.           Sampling frequency.                                                                            Y 74.25 MHz                                                                             G 74.25 MHz                                        G,B,R, or luminance signal                                                                     P 37.125 MHz                                                                            B 74.25 MHz                                        Each color difference signal                                                                   P 37.125 MHz                                                                            R 74.25 MHz                                                      (1)                                                                           The tolerance for the sampling frequencies should                             coincide with the tolerance for the line frequency of                         the relevant 1125/60 HDTV standard                              Form of coding                                                                              Uniformly quantitized PCM at least 8 bits per sample            Number of samples per digital                                                                  Y 1920    G 1920                                             active line:     P  960    B 1920                                             G,B,R or luminance signal                                                                      P  960    R 1920                                             Each color difference                                                         Analog-to-digital horizontal                                                                (2)                                                             timing relationship                                                                         88 Luminance clock periods                                      From end of digital active line                                               to the horizontal sync timing                                                 reference                                                                     Correspondence between video                                                  signal levels and the 8 most                                                  significant bits (MS8) of the                                                 quantization level for each                                                   sample:                                                                       Scale         0 to 255                                                        G,B,R, or luminance signal                                                                  220 quantization levels with the black level                                  corresponding to level 16 and the peak white level              Each color difference signal                                                                corresponding to level 235.                                                   The signal level may occasionally excurse beyond                              level 235.                                                                    226 quantization levels in the center part of the                             quantization scale with zero signal corresponding to                          level 126.                                                                    The signal level may occasionally excurse beyond                              level 16 and 240.                                               Code word usage for the 8 most                                                              Code words corresponding to quantization levels 0               significant bits (MSB)                                                                      and 255 are exclusively for synchronization. Levels                           1 to 254 are available for video.                             __________________________________________________________________________

                                      TABLE II                                    __________________________________________________________________________    Specifications            2. Audio Input                                                                (1) Analog signal                                                                        +4 dBm 600 OHMS/                         General Tape Type:        (line):    100K OHMS Switchable                     Recording/  1 Inch Metal Particle    Balanced 8 Circuits                      Playback Time:                                                                            Tape          (2) Analog Signal                                                                        Balanced 1 Circuit                       Power       63 Min. (11.76° Tool)                                                                (Cue):     XLRx4/D-Sub X1                           Requirements:                                                                             96 Min. (14.0° Tool)                                                                            Switchable                                           AC 100 V/117 V:10%                                                                          (3) Digital Signal                                  Power Consumption                                                                         50/60 Hz      (CCIR      ±0.3 Vp-p 75 OHMS                     Tape Transport Unit:      Recommendation 647)                                                                      1 Circuit                                Signal Processor Unit:                                                                    950 W Approx.                                                     Dimensions (W × H × D):                                                       1300 W Approx.                                                                              3. Sync Input:                                                                           1 Circuit                                Tape Transport Unit:      Tri-Level Bipolar                                               480 = 844 × 745 mm                                                                    Pulse Sync Signal:                                                                       R, G, B, Y, P.sub.B /P.sub.B             Signal Processor Unit:                                                                    (18-7/8 × 33-1/4 × 29-5/16 in)                                                             Switchable                                           48-730 × 615 mm                                                                       4. SMPTE Time Code                                                                       1.0 Vp-p 75 OHMS                         Weight:     (18-7/8 × 26-3/4 ×                                                              Input:     2 Circuits                               Tape Transport Unit:                                                                      24-3/16 in               Switchable                               Signal Processor Unit:    5. Video Output                                                                          (Video 0.7 Vp-p, Sync                    Ambient Temperature:                                                                      120 kg Approx. (265                                                                         (1) Analog Signal:                                                                       ±0.3 Vp-p)                                        lbs.)                                                             Video Sampling                                                                            110 kg Approx. (243      8-Bit Parallel (74.25                    Frequency Y:                                                                              lbs.)                    MHz)                                     P.sub.B /P.sub.B :                                                                        15°-35° C.                                                                    (2) Digital Signal                                                                       Multiplex 8-Bit Parallel                 Quantization:             Y:         (74.25 MHz)                              Frequency Bandwidth:                                                                      74.25 MHz                74.25 MHz                                Y:          37.125 MHz    P.sub.B /P.sub.B                                    P.sub.B /P.sub.B :                                                                        8 Bits/Sample            +4 dBm Low Impedance                     5/n:                      Clock:     Balanced 8 Circuits                      K Factor:   30 MHz ± 1.5 dB                                                                          6. Audio Output                                                                          +4 dBm Low Impedance                     Digital Audio (Ch1-Ch2)                                                                   15 MHz ± 1.5 dB                                                                          (1) Analog Signal                                                                        Balanced 1 Circuit                       Sampling Frequency:                                                                       56 dB         (Line):                                             Quantization:                                                                             Less Than 1 (2T Pulse)   XLRx4/D-Sub × 1                    Frequency Bandwidth:      (2) Analog Signal                                                                        Switchable                               Dynamic Range:                                                                            48 HAz        (Cue):                                              Crosstalk:  16 Bits/Sample           ±0.3 Vp-p 75 OHMS                                 20 Hz-20 KHz- (3) Digital Signal                                                                       2 Circuits                               Emphasis:   +0.5 dB/1.0 dB                                                                              (CCIR                                               T1:         Greater Than 90 dB                                                                          Recommendation 547)                                                                      2.4 Vp-p Low                             T2:         Less Than - 80 dB        Impedance                                Analog Audio (Cue                                                                         (1 KHz Between                                                                              7. Sync Output                                                                           600 OHMS Balanced                        Track) Frequency                                                                          Channels)     Tri-Level Bipolar                                                                        1 Circuit                                Response:                 Pulse Sync Signal:                                  S/N:        50 μS (On/Off Permitted)                                                                            1.0 Vp-p 75 OHMS                                     15 μS (On/Off Permitted)                                                                 8. SMFTE Time Code                                                                       1 Circuit                                Distortion                Output:                                                         100 Hz-12 KHz + 3 dB     1.0 Vp-p 75 OHMS                         Input/Output Signals                                                                      41 dB         9. Monitor Output                                                                        1 Circuit                                1. Video Input                                                                            (3% Distortion Level)                                                                       (1) Waveform                                        (1) Analog Signal:                                                                        Less than 3% (1 KHz,                                                                        Monitor Output Signal                                                                    ±0.3 Vp-p 75 OHMS                                 Operating Level)         1 Circuit                                                          (2) Video Monitor                                                                        ±0.3 Vp-p 75 OHMS                     (2) Digital Signal                                                                        R, G, B/Y, P.sub.B /P.sub.B                                                                 Output Signal                                                                            2 Circuits                               Y:          Switchable                                                        P.sub.B /P.sub.B                                                                          1.0 Vp-p 75 OHMS 1                                                                          (3) Monitor Sync                                                                         +4 dBm Low                                           Circuit       Output Signal (Tri-                                                                      Impedance                                Clock:      Video 0.7 Vp-p, Sync ±                                                                   Level):    Balanced 1 Circuit                                   0.3 Vp-p)                                                                                   (4) Audio Main Signal                                                                    1 Circuit                                            8-Bit Parallel (74.25                                                                       Monitor Output                                                  MHz)          (R)/(L): (Chosen                                                Multiplex 8-Bit Parallel                                                                    From DA1-DA8 &                                                  (74.25 MHz)   Cue)                                                            74.25 MHz                                                                                   10. Sync Output                                                               (525/60):                                           __________________________________________________________________________

Converter 160, according to the present invention converts an advancedtelevision or high definition television signal for recording orplayback on DVTRs 110 and 150. Converter 160 will be discussed inconjunction with FIGS. 2 and 3 followed by a detailed discussion inconjunction with FIGS. 4-10.

FIG. 2 illustrates converter 160 adapted for recording a televisionformat from HDTV source 210 on digital video recorder 160. HDTV source210 can be a high definition television camera or other known sourcesuch as a specialized high definition television video player.Preferably, RGB (red, green, blue) signals, a FORMAT V-DRIVE IN(vertical) synchronization signal and a FORMAT H-DRIVE IN (horizontal)synchronization signal are provided by HDTV source 210 (FIG. 6(a)).Matrix 211 converts the RGB signals to luminance signal Y andchrominance color difference signals R-Y and B-Y. Matrix 211 ispreferably constructed using resistors that combine the RGB signalaccording to the following equation:

    Y=0.731R+0.212G+0.087B

The chrominance signals are found as R-Y and B-Y using resistors andphase inverters. Other chrominance signals can alternatively beconverted such as I and Q associated with the video signal. Clock andcontrol circuit 230 clocks analog to digital converter 212 at afrequency f_(s) and >f_(s) where f_(s) is the sampling clock frequency.The luminance signal is digitized at the sampling frequency f_(s) andthe chrominance signals are digitized at the sampling frequency >f_(s).Because the two chrominance signals will later be combined into a singlechrominance signal, the chrominance signals are digitized at half therate of the luminance signal.

It is conceivable that HDTV source 210 could provide signals in eitheranalog or digital, RGB, or chrominance and luminance components. Thus,depending upon the particular output of the HDTV source, matrix 211 andanalog to digital converter 212 may not be required.

Clock and control circuit 230 also provides control signals toconversion memory 240. Data indicating the high definition televisionformat input by HDTV source 210 for recording on digital video recorder150 is input to clock and control circuit 230 for programming theconverter to provide control signals for the input HDTV format. Thisdata can be input by an operator manually selecting the format to beemployed or the format converter can be built for one specific format,for example, any format adopted by the United States. Based on the inputHDTV format type and the FORMAT H-DRIVE IN and FORMAT V-DRIVE INsynchronization signals, clock and control circuit 230 outputs read,write and timing signals to conversion memory 240, thus instructingconversion memory 240 to convert the HDTV input format to a formatsuitable for recording on digital video recorder 150. Conversion memorycontrol 230 controls conversion of the input HDTV format to luminanceand chrominance data signals in accordance with FIGS. 9 and 10 which mapdata into memory 240.

FIG. 3 illustrates converter 160 for converting the output of DVTR 110in playback mode, to an HDTV format displayed, for example, on displaymonitor 130. In playback mode, converter 160 controls the operation ofthe DVTR and provides synchronizing information with the output of theconverted video signal. Display 130 can be any output device such as amonitor, a cathode ray tube, liquid crystal display, projection screen,video cassette recorder, or other output, storage, conversion ortransmission device. Conversion memory 340 converts the digital signalsin accordance with control signals from clock and control circuit 230.Digital to analog converter 312 and matrix 311 perform the reversefunctions of matrix 211 and analog to digital converter 212. Furtherdetails of conversion memory 340 and digital to analog converter 312will be discussed subsequently in conjunction with FIG. 5. Furtherdetails of clock and control circuit 230 will be discussed inconjunction with FIG. 8.

FIG. 4 illustrates in greater detail the components of FIG. 2. FIG. 4particularly illustrates matrix 411, anti-aliasing filters 421-423, theindividual components of analog to digital converters 424-426, memories431-436 and multiplexer 440 during record mode. Matrix circuit 411converts an analog RGB input signal to luminance and color differencesignal outputs. Anti-aliasing low pass filters 421, 422 and 423 as wellas analog to digital converters 424, 425 and 426 are shown connected tothe outputs of matrix 411 B-Y, R-Y and Y, respectively. Write clockcontrol signal 401 from controller 230 clocks luminance analog todigital converter 426 at f_(s) and chrominance analog to digitalconverters 424 and 425 at >f_(s) via divide by two flip-flop 402.

Two memories are connected to the output of each analog-to-digitalconverter. memories 431 and 432 are connected to the output of B-Ychrominance analog to digital converter 424 under read/write control 403by controller 230. Likewise, memories 433 and 434 are connected to theoutput of R-Y chrominance analog to digital converter 425 and memories435 and 436 are connected to the output of luminance analog to digitalconverter 426 under read/write control 403 by controller 230. Read/writecontrol 403 from controller 230 controls alternatively read and writefunctions for the first and second memories connected to each analog todigital converter. For example, memory 431 alternatively reads andwrites with respect to memory 432 under control of read/write controlsignal 403. Read/write control signal 403 connects directly to the firstmemory, for example, and read/write control signal 403 inverted byinverter 404 connects to the second memory. Consequently, under controlof read/write control signa 403 from controller 230, digital videoinformation can be written into the one memory and simultaneously readout of the other memory. Controller 230 controls addressing of videodata written into and read out of the memories thereby performing adesired conversion between formats such as the conversion exemplified byFIGS. 7, 8, 9, and 10. Further details of the read/write clocking andcontrol will later be described in conjunction with FIGS. 6(a) and 6(b).

Multiplexer 440 combines the outputs of memories 431, 432, 433 and 434to yield a single chrominance signal. In particular, for the SonyHDD-1000 or Hitachi DVTR examples, the output of multiplexer 440 is an 8bit, byte-interleaved B-Y/R-Y chrominance data bit stream of 1920 bytesper line at a 59.94 Hz field rate. The field rate of 59.94 Hz isactually 60×(1000/1001) Hz. Multiplexer 440 is controlled by controller230 using a 74.175 MHz control signal to match the exemplary HDD-100074.175 megabyte per second data rate at a 59.94 Hz field rate. Becausethe chrominance memory outputs are multiplexed together, eachchrominance memory only needs to be half the size of each luminancememory. The outputs of memories 435 and 436 are thus sequentially readto provide a 8-bit luminance data bit stream of 1920 bytes per line andat a 59.94 Hz field rate. according to the Nyquist criterion, nospectral component of any signal should exceed one-half the digitizingclock frequencies f_(s) for luminance and 0.5 f_(s) for chrominance.Therefore, low pass filters 421-423 shown in FIG. 4 are used inconjunction with analog to digital converters 424-426, respectively. Thelow pass filters can also be called anti-aliasing filters. Low passfilter 423 on the luminance component preferably has a -3 dB drop offapproximately 0.4 f_(s). Low pass filters 421 and 422 on the twochrominance components should have a -3 dB drop off at approximately 0.2f_(s). The filters should not cut off extremely rapidly at the Nyquistfrequency of 0.5 f_(s) and 0.25 f_(s), respectively.

FIG. 5 illustrates in greater detail the components of FIG. 3. FIG. 5particularly illustrates conversion memory 340 (memories 531-536),digital to analog converter 312 (converters 524-526) and matrix 311(matrix 511) during playback mode. Read/write control 503 fromcontroller 230 controls memory pairs for alternating read and write.Luminance data from, for example, digital video player 110 isalternately written in memories 535 and 536. The chrominance signal fromdigital video player 110 is de-multiplexed by de-multiplexer 540 usingthe 74.175 MHz control signal from control circuit 230 for the 59.94 Hzfield rate. De-multiplexer 540 splits the chrominance signal into a B-Ysignal stored in memories 531 and 532 and a R-Y signal stored inmemories 533 and 534. Controller 230 controls the reading and writingfrom the memories to perform conversion back to the original HDTVformat. The conversion controlled by controller 230 is performed inresponse to a desired input HDTV format programmed into the controllersimilarly as the control discussed above in conjunction with FIG. 4.

After conversion to the digital HDTV format, the outputs of the memoriesare respectively fed to digital-to-analog converters 524, 525 and 526.The outputs of-the above-mentioned digital-to-analog converters arerespectively connected to low pass filter 523 having negligible responseat 0.5 f_(s) (about 38 MHz) and low pass filters 522, 521 havingnegligible response at 0.25 f_(s) (about 19 MHz). The outputs of lowpass filters 521, 522 and 523 feed through matrix 511 to produce an RGBhigh definition television output.

FIGS. 6(a) and 6(b) illustrate the clocking and control circuitry 230 toderive READ CONTROL, READ MEMORY RESET, WRITE CONTROL, WRITE MEMORYRESET and DVTR OUT synchronization control signals. FIG. 6(a) derivesthe signals for the record mode based on H-DRIVE IN and V-DRIVE IN froma broadcaster or proposed format source. In the record mode, theproposed format sampling rate f_(s) oscillator 931 is locked to thebroadcaster or proposed format source via phase locked loop PLL2 940.The DVTR is locked at DVTR frequency 74.175 MHz for the HDD-1000 byoscillator 930 locked to oscillator 931 via phase locked loop PLL1 941.FIG. 6(b) derives the signals for the playback mode wherein DVTRoscillator 930 drives the entire system like the broadcaster or proposedformat source drove the entire system in the record mode. DVTRoscillator 930 drives the DVTR via DVTR OUT at 74.175 MHz for theHDD-1000. DVTR oscillator 930 also controls the sampling frequency f_(s)oscillator 931 via phase locked loop PLL3 944.

FIG. 6(a) illustrates a generic depiction of the components for controlin the record mode. Oscillator 931 is locked to FORMAT H-DRIVE IN viaphase locked loop PLL2 940. Divide-by 967 divides down the output ofoscillator 931 by p for a comparison in phase locked loop comparator 940with the FORMAT H-DRIVE IN signal. The output of PLL2 comparator 940trims the frequency of crystal oscillator VCXO 931. The output ofcrystal oscillator VCXO 931 and the output of DVTR crystal oscillatorVCXO 930 are compared in phase locked loop PLL1 comparator 941. Theoutput of phase locked loop PLL1 comparator 941 trims the frequency ofcrystal VCXO 930. The output of oscillator 931 is divided by q individe-by 966 and the output of oscillator 930 is divided by r individe-by 960 before comparison in phase locked loop PLL1 comparator941.

The output of crystal VCXO 930 divided by t in divide-by 972 and dividedby s in divide-by 973 is combined by NAND gate 970 and set by flip-flop980 to yield the READ MEMORY RESET synchronization control signal. TheFORMAT H-DRIVE IN and FORMAT V-DRIVE IN are combined by NAND gate 971and set by flip-flop 981 to yield the WRITE MEMORY RESET synchronizationcontrol signal.

The DVTR OUT synchronization control signal of FIG. 6(a) drives theDVTR. The READ CONTROL and WRITE CONTROL synchronization control signalsclock memory address for i.e., luminance read memory 435 and luminancewrite memory 436, respectively. Memories 431-436 are addressed byaddress counters (not shown). The address counters are programmed tocount up to the number of necessary storage spaces required forconversion. The READ MEMORY RESET and WRITE MEMORY RESET synchronizationcontrol signals reset i.e., luminance read memory 435 and luminancewrite memory 436, respectively. When a memory is reset by a READ or aWRITE MEMORY RESET synchronization control signal, the signal'sassociated memory resets to a reference storage space--such as theupper-left corner of the frame.

VCXO oscillators 931 and 930 are preferably crystal oscillators. Acrystal oscillator has a crystal ground to produce a very stable andaccurate frequency. The oscillation frequency of the crystal can becontrolled by a voltage controlled capacitor (varicap) or similarreactive means. Such an arcuate crystal oscillator is an idealoscillator for accurate phase locked loop (PLL) frequency control. As analternative to crystal VCXO oscillators, microprocessor controloscillators can be used in the event a microprocessor controlledoscillator is available having a frequency stability comparable to thatof a crystal VCXO.

FIG. 6(b) illustrates a generic depiction of the components for controlin the playback mode. Sampling frequency, crystal oscillator VCXO 931and DVTR crystal oscillator VCXO 930 are compared in phase locked loopcomparator PLL3 944 to control the frequency of oscillator 931. Theoutput of phase locked loop PLL3 comparator 944 trims the frequency ofoscillator 931. The output of oscillator 931 is divided by q individe-by 966 and the output of oscillator 930 is divided by r individe-by 960 before comparison in phase locked loop comparator 944.

The DVTR H-DRIVE IN and DVTR V-DRIVE IN are combined in NAND gate 974and set by flip-flop 982 to yield the WRITE MEMORY RESET synchronizationcontrol signal. The output of crystal VCXO 931 divided by 2p individe-by 976 by n in divide-by 977 is combined in NAND gate 975 and setby flip-flop 983 to yield the READ MEMORY RESET synchronization controlsignal.

The DVTR OUT synchronization control signal of FIG. 6(b) drives theDVTR. The READ CONTROL and WRITE CONTROL synchronization control signalsclock memory addresses for i.e., luminance read memory 535 and luminancewrite memory 536, respectively. Memories 531-536 are addressed byaddress counters. The address counters are programmed t count up to thenumber of necessary storage spaces required for conversion. The READMEMORY RESET and WRITE MEMORY RESET synchronization control signalsreset, i.e., luminance read memory 535 and luminance write memory 536,respectively. When a memory is rest by a READ or a WRITE MEMORY RESETsynchronization control signal, the signal's associated memory resets toa reference storage space--such as the upper-left corner of the frame.

In the above, the addressed memory can be a random access memory in sizedependent upon the number of DVTR lines necessary for a completesequence of chrominance and luminance lines. instead of a random accessmemory, the memory can be a sequential address memory. The READ and theWRITE MEMORY RESET pulses from the NAND gates can be used to reset thesequential access memory, the dummy samples illustrated in FIGS. 7 and 8preferably should be inserted between lines during the time of thehorizontal interval. Therefore, from FIG. 7, dummy sample 612 should beinserted between lines 610 and 611 at 612a; dummy sample 614 should beinserted between lines 611 and 613 at 614a; dummy sample 617 should beinserted between either/or lines 613 and 615 or lines 615 and 616 at 61aand/or 617b; dummy sample 619 should be inserted between lines 616 and618 at 619a; and dummy sample 621 should be inserted between dummysamples 618 and 620 at 621a. By inserting the dummy samples betweenlines, the dummy samples can be stored in the sequential access memoryduring the horizontal interval. When using a random access memory, thedummy samples do not need to be placed at the end of a line for they canbe randomly accessed or even skipped over by the addressing circuitry atany point in time.

Among the proposed HDTV formats, three exemplary source televisionformats are described herein. These exemplary source formats areexamples for teaching the present invention. They are in no waypreferred over each other or over any other source format. The firstexemplary source format is representable as 1370 luminance (Y) samplesper line of video signal and 685 chrominance (R-Y and B-Y) samples perline of video signal. Proper digital representation for the firstexemplary source format may require 1370 samples. This format has anactive line time of approximately 17.8 microseconds and a RGB signalbandwidth is 28.9 MHz. Accordingly, the minimum number of samples peractive line to accurately reproduce the luminance signal is2.5×28.9×17.8 or 1286 samples. The factor 2.5 allows for practicalNyquist frequency filter rolloff, corresponding to the 1/0.4 factordiscussed elsewhere in this text.

In accordance with FIGS. 7 and 8, for the first source HDTV format, thememories 435 and 436 are written into and read out of in a mannercorresponding to the 1920 samples per line permitted by the exemplaryHDD-1000 DVTR. An entire 1370 sample first luminance line 610, a firstportion of 548 samples of a second luminance line 611 and 2 dummysamples 612 make up DVTR line #1, to be stored in memory 435 and 436. Asecond portion of 822 samples of the second luminance line 611 a firstportion of 1096 samples of a third luminance line 613 and 2 dummysamples 614 make up DVTR line #2. A second portion of 274 samples of thethird luminance line 613, an entire 1370 sample fourth luminance line615 and a first portion of 274 samples of a fifth luminance line 616 and2 dummy samples 617 make up DVTR line #3. A second portion of 1096samples of the fifth luminance line 616, a first portion of 822 samplesof a sixth luminance line 620 and 2 dummy samples make up DVTR line #4.A second portion of 548 samples of the sixth luminance line 618, anentire 1370 sample seventh luminance line and 2 dummy samples make upDVTR line #5. DVTR line #6 begins with a next entire 1370 sample line,thus repeating the above sequence of seven luminance lines every fiveDVTR lines. The partitioning of luminance lines and the number of dummysamples are chosen to adapt a given number of luminance lines into agiven number of DVTR lines and thus have a predictable repeatingpattern, thus minimizing memory size.

Alternatively, the dummy samples may be located between lines,especially in the instance of a sequential access memory. Thus, dummysamples 612 may be located at location 612a, dummy samples 614 atlocation 614a, and so on during the time of the horizontal blankinginterval.

FIG. 8 illustrates an 685 sample R-Y or B-Y chrominance line 710corresponding to 1370 sample luminance line 610 of the first sourceformat illustrated in FIG. 7. FIG. 8 illustrates the conversion ofsource lines to DVTR lines output of either memories 433 and 434 for B-Ychrominance lines and memories 431 and 432 for R-Y chrominance lines.Because the R-Y and B-Y chrominance lines are multiplexed together bymultiplexer 440, the number of samples of each chrominance source line(685 samples) are half that of each luminance source line (1370samples). Thus, partitioning of the chrominance source lines and the useof dummy samples in FIG. 8 is similar to FIG. 7.

As described in connection with FIG. 7, dummy samples may be insertedbetween lines at locations 712a, 714a, 717a, 717b, 719a, 721a and so on.

Depending on the source format recorded, any number of dummy samples,including zero dummy samples per line, are possible when thepartitioning of source lines is chosen. The dummy samples are notnecessary for conveying information but may convey useful information bytheir use as additional luminance and chrominance data, parity bits, assynchronization bits, as memory row identification bits or the like. Forexample, the dummy samples can be used to indicate the beginning of eachnew frame. In the event the DVTR should drop data or lose sync, thedummy sample would permit quick correction of the error. Dummy samplescan also be used to indicate the beginning of a new frame when theconverted format is interlaced at i=2, for example, for correction inthe event of an error.

FIG. 9 illustrates how the seven luminance or chrominance source linesfor the first exemplary source format are fit into five DVTR lines. DVTR110, for example, of FIG. 3 dictates the DVTR lines and display 130, forexample, dictates the source lines. Note that after a predeterminednumber of source or DVTR lines, the source and DVTR line patternrepeats.

FIG. 10 illustrates a second exemplary source format having 2055 samplesper line. Note that after a predetermined number of fourteen sourcelines and fifteen DVTR lines, the pattern repeats. The exemplary sourceformat of FIG. 10 also uses 2 dummy samples per DVTR tape line.

FIG. 11(a) is a flowchart illustrating the following method steps 1-11according to a first embodiment of FIG. 11(b) is a flowchartillustrating the following method steps 1-11 according to a secondembodiment. Any proposed format can be realized in a programmableconverter as described below:

DIGITAL VIDEO TAPE RECORDER (DVTR) VARIABLES Given for a DVTR:

1) the number of total lines per frame (N_(DT)),

2) the number of active lines per frame (N_(Sa)),

3) the number of total luminance samples (bytes) per line (N_(DTL)),

4) the number of active luminance samples (bytes) per line (N_(DL)),

5) a DVTR field rate (fields per second) equal to the proposed formatfield rate (f_(vd) =f_(v)),

6) the interlace characteristic of the DVTR i_(d) 1:1=1 field/frame1:2=2 fields/frame 1:3=3 fields/frame . . . !, and

7) f_(sD) number of active luminance samples per second

SOURCE FORMAT VARIABLES

Given for a source format:

a) the number of total lines per frame (N_(T)),

b) the number of active lines per frame (N_(s)),

c) a source format field rate (fields per second) equal to the DVT fieldrate (f_(v) =f_(vd)),

d) the interlace characteristic of the source format i 1:1=1 field/frame1:2=2 fields/frame 1:3=3 fields/frame . . . !, and

e) the minimum number of luminance samples (bytes) per line (N_(L--) /

STEPS FOR DERIVING THE NUMBER OF DUMMY SAMPLES ACCORDING TO A FIRSTEMBODIMENT

Step #1, Determine the number of active lines in a field of the DVTR andthe number of active lines in a field of the source format. ##EQU1##Step #2, Determine the number of active luminance samples (bytes) perfield for the DVTR

    B=N.sub.DL N.sub.Da field

Step #3, Determine the number of active luminance samples of the sourceformat samples (bytes) to arrange on a DVTR active line (N_(c)) ##EQU2##

The result N_(c), will not always be an integer. N_(c) must be aninteger because a digital sample (byte) can only be an integer,

Step #4. If N, is not an integer, decrement N_(DL) by 1 and go to step#2.

When N_(c) becomes an integer, the number of ties N_(DL) is decremented,n_(dcc), equals the number of dummy samples that will be used on eachline.

Preferably, the integer N_(c) will be an even number as N_(c) /2 will bethe number of chrominance samples which preferably is an integer. Evennumbers will be easier to divide by two in order to clock the 0.5 f_(s)chrominance analog-to-digital and digital-to-analog converters. However,if an odd integer N_(c) is used, the circuitry will tolerate droppingone sample at the edge of every other line. Anti-aliasing low passfilters 421, 422, 521, 522 will also minimize any effects of the droppedhalf cycle.

N_(c) thus equals the number of active luminance samples (bytes) 610 ofa source active format luminance (Y) line placed on a DVTR line. Thenumber of active samples (bytes) 710 of a source active formatchrominance (R-Y) line or (B-Y) line placed on a DVTR line thus equals>N_(c) because the chrominance component is divided in half bymultiplexers 440 and 540 for the chrominance lines. The linearrangements of FIGS. 7 and 8 can thus be determined from the calculatedN_(c) samples (bytes) placed among the repeated lines. The N_(c) samplesare placed among the lines with n_(dcc) dummy samples at the end of eachline. Eventually a pattern will repeat over and over after a number oflines (five lines for the first exemplary source format, fourteen linesfor the second exemplary source format and five lines for the thirdexemplary source format).

STEPS FOR DERIVING THE NUMBER OF DUMMY SAMPLES ACCORDING TO A SECONDEMBODIMENT

Step #1, Determine the number of active lines in a field of the DVTR andthe number of active lines in a field of the source format. ##EQU3##Step #1A, Determine the ratio (R) of active lines in a field of the DVTRto active lines in a field of the source format. ##EQU4## Step #2, Finda ratio (j/k) of integers that closely approximate but do not exceed R.The ratio should be selected so that the number of stored lines j ismanageable.

The source active format lines will be stored in j lines of memory, eachline of memory being N_(DL) samples (bytes) in length. As j directlyexpresses the size of the memory, it is desirable to minimize the valueof j. The smaller the ratio j/k, the lesser the cost of the memory. Avalue for j of at least about 16 is desirable for inexpensive digitalconstruction.

Step #3, Determine the number of active luminance samples (bytes) peractive DVTR line. ##EQU5##

If N_(c) is not an integer, some number of d of dummy samples must beadded to the real active luminance bytes to comprise a total of N_(DL)active luminance samples (bytes) per active line to be recorded.

Step #4, If N_(c) is not an integer, round down to find the largestinteger (less than b) which when multiplied by k/j yields an integer i.

When N_(c) becomes an integer, the number of dummy samples d that willbe used on each line is d=N_(DL) -i.

Now that the memory arrangement and number of dummy samples for eachDVTR line has been determined by either of the above embodiments, how toprovide oscillators for generating the clock and control signals and howto control the oscillators will be discussed below.

STEPS FOR DERIVING f_(c), p, q and r

The active portion of a television line is approximately 85% of thetotal line time.

Step #5, Determine the total number of source format luminance samplesto be stored per active DVTR line ##EQU6##

The result, N, will not always be an integer. In order for digitalgeneration, N, must be an integer.

Step #6, Round N to the nearest integer.

In effect, by rounding the approximated 85% blanking time is slightlyvaried up or down until the nearest integer for N is arrived at.

For accurate PLL oscillator control, a small number of low primeintegers are desired to divide the oscillator outputs before comparisonin the PLL comparator. The preferred integers are the remaining factorsderived from the above divided N and from the number of total luminancesamples per line N_(DTL).

Step #7, Factor N_(DTL).

Step #8, Factor N. Check for common factors of N_(DTL) and N.

Step #9, Increment and decrement N and jump to step #7 until the numberof common factors of N_(DTL) and N is greatest.

Alternatively, N N_(T) and N_(DTL) can be factored. Then N can beincremented and decremented until the number of common factors of NN_(T) and N_(DTL) N_(DT) is greatest.

Step #10, Compute the sampling frequency oscillator rate (f_(s)) insamples per second.

    f.sub.s =N N.sub.T f.sub.v

The incrementing and decrementing of N should only be performed withinreasonable limits in order to provide a frequency for PLL comparisonyielding less error than an oscillator PLL driven by dividers of manyuncommon factors. If N=N_(DTL), the two oscillators will be at the samefrequency and a PLL is not required (i.e., 900 line, 59.94, 1:1,n=1200). Choosing a value for N may be performed in an iterative processuntil the designed circuit achieves an acceptable cost and accuracytradeoff.

Step #11, Solve the following equation for q and r by first cancelingcommon factors. ##EQU7## Then take q as the remaining factors of (NN_(T) /i) and r as the remaining factors of (N_(DTL) N_(DT) /i_(D)).

N itself will be designated p for purposes of FIGS. 6(a) and 6(b),12(a)-14(b), and 16(a) and 16(b). As discussed in conjunction with FIGS.6(a) and 6(b), 12(a)-14(b), and 16(a) and 16(b), the remaining factorsderived from N_(DTL) and N are thus used as divide by factors p, q, andr for accurate frequency comparison by the phase locked loops.

Also, for purposes of FIGS. 6(a) and 6(b), 12(a)-14(b), and 16(a) and16(b), t=N_(DTL), s=f_(sD) /f_(v), and n=2(N_(T))(p).

THE DVTR VARIABLES DEFINED

The Sony HDD-1000 DVTR and the Hitachi DVTR have the followingparameters:

1) N_(DT) =1125 total lines per frame

2) N_(Da) =1035 active lines per frame

3) N_(DTL) =2200 total luminance samples (bytes) per line

4) N_(DL) =1920 active luminance samples (bytes) per line

5) f_(v) =59.94 fields per second (or 60.--operator selectable.)

6) i_(D) =2 fields per frame

7) f_(sD) =74.175 MHz

Other DVTRs can also be used.

STRUCTURING THE CONVERTER PARAMETERS FOR A FIRST EXEMPLARY SOURCE FORMATACCORDING TO THE FIRST EMBODIMENT

A first exemplary source format has the following parameters:

a) N_(T) =787.5 total lines per frame

b) N_(a) =720 active lines per frame

c) f_(v) =59.94 fields per second

d) i=1 field per frame

Step #1, N_(Da) field =N_(Da) /i_(D) =1035 active lines per frame/2fields per frame=517.5 active lines per field, N_(a) field =N_(a) /i=720active lines per field/1 field per frame=720 active liens per field.

Note that the HDD-1000 DVTR records 1035 active liens per frame as 517active lines in a first field and 518 active lines in a second field.Nevertheless, N_(Da) field is calculated as 517.5 active lines per fieldfor determining converter parameters according to the present invention.Well-known control circuitry is used to store the correct number ofactive lines in the appropriate DVTR field as required by the HDD-1000DVTR.

Step #2, B=N_(DL) N_(Da) field =(1920 active luminance samples (bytes)per line) (517.5 active lines per field)=993,600 active luminancesamples (bytes) per field.

Step #3, N_(c) =B/N_(a) field =(993,600 active luminance samples (bytes)per field)/(720 active liens per field=1380 active luminance samples(bytes) per active line.

Step #4, N_(c) is thus an integer and n_(ddc) =0 dummy samples.

Step #5, N=N_(c) /0.85=(1380 active luminance samples (bytes) per activeline)/0.85=1623.592412 total luminance samples (bytes) per active DVTRline.

Step #6, N=1624 total luminance samples (bytes) per active DVTR line,rounded to the nearest integer.

Step #7, N_(DTL) =2200=2×2×2×5×5×11.

Step #8, N=1624=2×2×2×7×29. 1624 factors poorly and has few commonfactors with N_(DTL).

Step #9, increment and decrement N until the number of common factors ofN_(DTL) and N is greatest. Take the larger factors of 2200, like 11, 5and 2. Look for numbers close to 1624 (but not 1624) that have factorswith 11, 5, 5 and 2 in them. 550=11×5×2. 2200/550=4. 4-1=3.1×5×5×2×3=1650. Therefore, an N of 1650 would work. Also, if factorswith 11.5 and 5 were tried instead, 275=11×5×5, 2200/275=8, 8-1=7 (sevenis not a lowest prime to settle at just yet), 8-2=6=3×2, 11×5×2×3=1650.Therefore, N=1650 is used.

Step #10, f_(s) =N N_(T) f_(v) =(1650 total samples (bytes) per DVTRline) (787.5 total lines per frame) (59.94 fields persecond)=77.88461538 MHz.

Step #11, ##EQU8##

The product of the remaining factors of (N_(DTL) N_(DT) /i_(D)), 5, 2and 2, equals 20 and is designated r. The product of the uncommonfactors N, 3 and 7, equals 21 and is designated q. N itself, 1650, isdesignated p. The control circuitry can be built for the first sourceformat by conforming the circuitry of FIGS. 6(a) and 6(b) with the abovecalculated variables. The control circuitry of the preferred embodimentfor the first exemplary source format as illustrated in FIGS. 12(a) and12(b) is built as calculated according to the second embodiment below.In the second embodiment, when j/k is selected as 5/7 instead of 23/32,a smaller memory size is achieved having two dummy samples. Dummysamples may be necessary when converting an interlaced format and/or foralleviating data errors. In a high volume commercial application, thevariables determined by the first and second embodiment may need to bevaried in order to achieve the lowest necessary memory capacity for thelowest cost per converter. When designing such a converter, an iterativedesign approach to using the first and second embodiments is necessaryfor the best tradeoff.

STRUCTURING THE CONVERTER PARAMETERS FOR A FIRST EXEMPLARY SOURCE FORMATACCORDING TO THE SECOND EMBODIMENT

Step #1, N_(da) field=N_(Da) /i_(D) =1035 active lines per frame/2fields per frame=517.5 active lines per field, N_(a) field =N_(a) /i=720active lines per field/1 field per frame=720 lines per field.

Step #1A, R=j/k=N_(Da) field /N_(a) field =517.5/720=0.71875

Step #2, j/k=23/32, select a smaller ratio j/k that approximates 23/32so that the memory size j is at most 16 (design choice for thisexample). Let j/k=5/7.

Step #3, N_(c) =(j/k) N_(DL) =(5/7) (1920 active luminance samples(bytes) per line)=1371.428571 active luminance samples (bytes) perline.)

Step #4, N_(c) is not an integer, round down N_(c) to 1371, (7/5)(1371)=1919.4 which is not an integer, round down N_(c) to 1370, (7/5)(1370)=1918 which is an integer. Therefore N_(c) =1370 and d=1920=1918=2dummy bytes per line.

Step #5, N=N_(c) /0.85=(1370 active luminance samples (bytes) perline)/0.85=1611.76406 total luminance samples (bytes) per DVTR line.

Step #6, N=1612 total samples (bytes) per DVTR line, rounded to thenearest integer.

Step #7, N_(DTL) =2200=2×2×2×5×5×11.

Step #8, N=1612=2×2×13×31. 1624 factors poorly and has few commonfactors with N_(DTL).

Step #9, increment and decrement N until the number of common factors ofN_(DTL) and N is greatest. Take the larger factors of 2200, like 11.5and 2. Look for numbers close to 1612 (but not 2200) that have factorswith 11, 5, 5 and 2 in them. 550=11×5×5×2. 1612/550=2.93.11×5×5×2×3=1650. 1650 is not closest. Try numbers that have 5×2×2 inthem. 5×2×2=20. 2200/20=100. 1612/20=80.6 5×2×2×81=1620. ThereforeN=1620 is used.

Step #10, f_(s) =N N_(T) f_(v) =(16210 total samples (bytes) per DVTRline) (787.5 total lines per frame (59.94 fields per second)=76.468455MHz.

Step #11 ##EQU9## The product of the remaining factors of (N_(DTL)N_(DT) /i_(D)), 5, 5, 2 and 11, equals 550 and is designated r. Theproduct of the uncommon factors of N, 3, 3, 3, 3 and 7, equals 567 isdesignated q. N itself, 1620, is designated p. t=N_(DTL) =220, s=f_(sD)/f_(v) =1237487, 2p=3240, n=2(N_(T) (p)=2(787.5)(1620)=2551500. Thecontrol circuitry can be built for the first source format by conformingthe circuitry of FIGS. 6(a) and 6(b) with the above calculatedvariables. FIGS. 12(a) and 12(b) show such circuitry connected per theabove calculated values.

STRUCTURING THE CONVERTER PARAMETERS FOR A SECOND EXEMPLARY SOURCEFORMAT ACCORDING TO THE FIRST EMBODIMENT

A second exemplary source format has the following parameters:

a) N_(T) =525 total lines per frame

b) N_(s) =483 active lines per frame

c) f_(v) =59.94 fields per second

d) i=1 field per frame

Step #1, N_(Da) field =N_(Da) /i_(D) =1035 active lines per frame/2fields per frame=517.5 active lines per field, N_(a) field =N_(a) /i=483active lines per field/1 field per frame=483 active lines per field.

Step #2, B=N_(DL) N_(Da) field =(1920 active luminance samples (bytes)per active line (517.5 active lines per field)=993,600 active luminancesamples (bytes) per field.

Step #3, repeated N_(c) =B/N_(a) field =(993,082.5 active luminancesamples (bytes) per field)/(483 active lines per field)=2056.07149active luminance samples (bytes) per active line.

Step #4, repeated, N_(c) is not an integer. Again decrement N_(DL) by 1,N_(DL) =1918 active luminance samples (bytes) per active line andn_(dcc) =2. Go back to step #2.

Step #2, repeated again, B=N_(DL) N_(Da) field =(1918 active luminancesamples (bytes) per line (517.5 active lines per field)=992,565 activeluminance samples (bytes) per field.

Step #3, repeated again, N_(c) =B/N_(a) field =(992,565 active luminancesamples (bytes) per field)/(483 active lines per field)=2055 activeluminance samples (bytes) per active line. Therefore, n_(dcc) =2 andthere will be two dummy samples (bytes). N_(c) =2055 samples of a sourceformat luminance (Y) line will be placed on the N_(DL) =1920 sample DVTRline by placing 1920 active luminance samples on a first DVTR line and2055-1920=135 active luminance samples on a second DVTR line. The numberof chrominance R-Y placed will be >N_(c) =1027 samples and chrominanceB-Y will be also >N_(c) =1027 samples (one half a sample is dropped dueto an odd N_(c)).

Step #5, N=N_(c) /0.85=(2055 active luminance samples (bytes) per activeline)/0.85=2417.647059 total luminance samples (bytes) per active DVTRline.

Step #6, N=2418 total luminance samples (bytes) per DVTR line, roundedto the nearest integer.

Step #7, N_(DTL) =2200=2×2×2×5×5×11.

Step #8, N=2418=2×3×13×31.2418 factors poorly and has few common factorswith N_(DTL).

Step #9, increment and decrement N until the number of common factors ofN_(DTL) and N is greatest. Take the larger factors of 2200, like 11, 5and 2. Look for numbers close to 2418 (but not 2200) that have factorswith 11, 5, 5 and 2 in them. 550=11×5×5×2. 2200/550=4. 4+1=5.11×5×5×2×5=2750. Therefore, an N of 2750 would work. But, a numbercloser to 2418 is preferred. Look for numbers close to 2400 (but not2200) that have factors with 2×2×2×5×5 in them. 200=2×2×2×5×5.2200/200=11. 11-1=10=2×5. 2×2×2×5×2×5=2000. 11+1=12=3×2×2.2×2×2×5×5×3×2×2=2400. 2400 is very close to 2418. Therefore N=2400.

Step #10, f_(s) =N N_(T) F_(v) =(2400 total samples (bytes) per line)(525 total lines per frame)(59.94 fields per second)=75.52447552 MHz.

Step 11, ##EQU10##

The product of the uncommon factors of (N_(DTL) N_(DT) /i_(D)), 11 and5, equals 55 and is designated r. The product of the uncommon factors of(N N_(T) /i), 2, 2, 2 and 7, equals 56 and is designated q. N itself,2400, is designated p. t=N_(DTL) -2200, s=f_(sD) /f_(v) =1237487,2p=4800=2(N_(T))(p)=2(525)(2400)=2520000. The control circuitry can bebuilt for the second source format by conforming the circuitry of FIGS.6(a) and 6(b) per the above calculated values. FIGS. 13(a) and 13(b)show such circuitry connected as calculated above except that, to savecosts in the preferred embodiment, the values of q and r have beenmultiplied by ten so that r=550 for both the first and second exemplarysource formats. Multiplying the values of q and r by ten, however, willdecrease the frequencies compared at PLL1 941 and PLL3 thus decreasingthe frequency control stability.

STRUCTURING THE CONVERTER PARAMETERS FOR A SECOND EXEMPLARY SOURCEFORMAT ACCORDING TO THE SECOND EMBODIMENT

Step #1, N_(Da) field =N_(Da) field /i_(D) =1035 active lines perframe/2 fields per frame -517.5 active lines per field, N_(a) field=N_(s) /i=483 active lines per field/1 field per frame=483 active linesper field.

Step #1, R=N_(Da) field /N_(a) field =51.5/483=1.071428571.

Step #2, j/k=15/14. j=15 stored lines is a manageable number.

Step #3, N_(c) =(j/k) N_(DL) =(15/14) (1920 active luminance samples(bytes) per line)=2057.142857 active luminance samples (bytes) per line.

Step #4, N_(c) is not an integer. 2057×(14/15)=1919.866667.2056×(14/15)=1918.933333. 2055×(14/15)=1918. Therefore, N_(c) =2055active luminance samples (bytes) per line and d=1920-1918=2 dummysamples per line.

Step #5, N=N_(c) /0.85=(1918 active luminance samples (bytes) perline)/0.85=2417.647059 total luminance samples (bytes) per DVTR line.

Step #6, N-2418 total samples (bytes) per DVTR line, rounded to thenearest integer.

Step #7, N_(DTL) =2200=2×2×2×5×5×11.

Step #8, N=2418=2×3×13×31. 2418 factors poorly and has few commonfactors with N_(DTL).

Step #9, increment and decrement N until the number of common factors ofN_(DTL) and N is greatest. Take the larger factors of 2200, like 11, 5and 2. Look for numbers close to 2418 (but not 2200) that have factorswith 11, 5, 5 and 2 in them. 550=11×5×5×2. 2418/550=4.3966.11×5×5×2×4=2200. 11×5×5×2×5=2750. But, a number closer to 2418 ispreferred. Also, if factors with 11, 5, 2 and 2 were tried instead,220=11×5×2×2, 2418/220=10.9909. 11×5×2×2×11=2420. We have few commonfactors with 11. Look for numbers close to 2418 (but not 2200) that have2, 2, 2, 2, 2, 3 in them. 2×2×2×2×2×3=96. 2418/96=24.1875. 24=3×2×2×2,2×2×2×2×2×3×3×2×2×2=2304. Try for a higher number of common factors. Upto 24 to 25. 25=5×5. We need fives. 2×2×2×2×2×3×5×5=2400.

Step #10, f_(s) =N N_(T) f_(v) =(2400 total samples (bytes) per DVTRline) (525 total lines per frame) (59.94 fields per second)=75.52447552MHz.

Step 11, ##EQU11##

The product of the common factors N_(DTL) N_(DT) /i_(D)), 11 and 5,equals 55 and is designated r. The product of the uncommon factors (NN_(T) /i), 2, 2, 2 and 7, equals 56 and is designated q. N itself, 2400,is designated p. t=N_(DTL) =2200. s=f_(sD) /f_(v) =1237487, 2p=4800,n=2(N_(T))(p)=2(525)(2400)=2520000. The control circuitry can be builtfor the second source format by conforming the circuitry of FIGS. 6(a)and 6(b) per the above calculated values. FIGS. 13(a) and 13(b) showsuch circuitry connected as calculated above except that, to save costsin the preferred embodiment, the values of q and r have been multipliedby ten so that r-550 for both the first and the second exemplary sourceformats. Multiplying the values of q and r by ten, however, willdecrease the frequencies compared at PLL1 941 and PLL3 944 thusdecreasing frequency control stability.

STRUCTURING THE CONVERTER PARAMETERS FOR A THIRD EXEMPLARY SOURCE FORMATACCORDING TO THE FIRST EMBODIMENT

A third source format has the following parameters:

a) N_(T) =900 total lines per frame

b) N_(a) =828 active lines per frame

c) f_(v) =59.94 fields per second

d) i=1 field per frame

Step #1, N_(Da) field =N_(Da) /i_(D) =1035 active lines per frame/2fields per frame=517.5 active lines per field, N_(a) field =N_(a) /i=828active lines per field/1 field per frame=828 active lines per field.

Step #2, B=N_(DTL) N_(Da) field =(1920 active luminance samples (bytes)per line) (517.5 active lines per field)=993,600 active luminancesamples (bytes) per field.

Step #3, N_(c) =B/N_(a) field =(993,600 active luminance samples (bytes)per field)(828 active lines per field)=1200 active luminance samples(bytes) per active line.

Step #4, N_(c) is an integer, therefor n_(dcc) =0 and there will be nodummy samples (bytes). N_(c) =1200 active luminance samples of aproposed format luminance (Y) line will be placed on a N_(DL) =1920active luminance sample DVTR line. The number of chrominance R-Y placedwill be >N_(c) =600 samples and chrominance B-Y will be also >N_(c) =600samples.

Step #5, N=N_(c) /0.85=(1200 active luminance samples (bytes) perline(/0.85=1411.764706 total luminance samples (bytes) per DVTR line.

Step #6, N=1412 total luminance samples (bytes) per DVTR line, roundedto the nearest integer.

Step #7, N_(DTL) =2200=2×2×2×5×5×11.

Step #8, N=1412=2×2×353. 1412 factors poorly and has few common factorswith N_(DTL).

Step #9, increment and decrement N until the number of common factors ofN_(DTL) and N is greatest. Take the larger factors of 2200, like 11, 5and 2. Look for numbers close to 1412 (but not 2200) that have factorswith 11, 5, 5 and 2 in them. 550=11×5×5×2. 2200/550=4. 4-1=3.311×5×5×2×3=1650. Therefore, an N of 1650 would work. But, a numbercloser to 1412 is preferred. Also, if factors with 11, 5 and 5 weretried instead, 275=11×5×5, 2200/275=8, 8-1=7 (seven is not a lowestprime to settle at just yet), 8-2=6=3×2, 11×5×5×3×2=1650. If we used 8-3then 11×5×5×5=1375 which would work better since it is very close to1412. Therefore, N=1375 is used and in fact yields an f_(s) equal to theDVTR clock, and thus oscillator 931 is not needed for this format. Thissimplifies the circuitry and eliminates any jitter associated with twophase locked loops in cascade.

Step #10, f_(s) =N N_(T) f_(v) =(1375 total luminance samples (bytes)per DVTR line) (900 total lines per frame) (59.94 fields persecond)=74.17582418 MHz.

Step 11, ##EQU12##

There are no remaining factors. Hence q=r=1 and f_(s) =74.17582418 MHzwhich is the same sampling frequency as the DVTR. Oscillators 930 and931 can be the same oscillator. N itself, 1375, is designated p.t=N_(DTL) =2200, s=f_(sD) /f_(v) =123787, 2p=2750,n=2(N_(T))(p)=2(900)(1375)=2475000. The control circuitry can be builtfor the second source format by conforming the circuitry of FIGS. 6(a)and 6(b) per the above calculated values. FIGS. 14(a) and 14(b) showsuch circuitry connected as calculated above.

STRUCTURING THE CONVERTER PARAMETERS FOR A THIRD EXEMPLARY SOURCE FORMATACCORDING TO THE SECOND EMBODIMENT

Step #1, N_(Da) field =N_(Da) /i_(D) =1035 active lines per frame/2fields per frame=517.5 active lines per field, N_(a) field =N_(a) /i=828active lines per field/1 field per frame=828 active lines per field.

Step #1A, R=N_(Da) field /N_(a) field =517.5/828=0.625.

Step #2, j/k=5/8. j=5 lines is a manageable number.

Step #3, N_(c) =(j/k) N_(DL) =(5/8)(1920 active luminance samples(bytes) per line)=1200 active luminance samples (bytes) per line.

Step #4, N_(c) is an integer. Therefore, N_(c) =1200 active luminancesamples (bytes) per line and d=0 dummy samples per line.

Step #5, N=N_(c) /0.85=(1200 active luminance samples (bytes) perline(/0.85=1411.764706 total luminance samples (bytes) per DVTR line.

Step #6, N=1412 total luminance samples (bytes) per DVTR line, roundedto the nearest integer.

Step #7, N_(DTL) =2200=2×2×2×5×5×11.

Step #8, N=1412=2×2×353. 1412 factors poorly and has few common factorswith N_(DTL).

Step #9, increment and decrement N until the number of common factors ofN_(DTL) and N is greatest. Take the larger factors of 2200, like 11, 5and 2. Look for numbers close to 1412 (but not 2200) that have factorswith 11, 5, 5 and 2 in them. 550=11×5×5×2. 2200/550=4. 4-1=3.11×5×5×2×3=1650. Therefore, an N of 1650 would work. But, a numbercloser to 1412 is preferred. Also, if factors with 11, 5 and 5 weretried instead, 275=11×5×5, 2200/275=8, 8-1=7 (seven is not a lowestprime to settle at just yet), 8-2=6=3×2, 11×5×5×3×2=1650. If we used8-3=5 then 11×5×5×5=1375 which would work better since it is very closeto 1412. Therefore, N=1375 is used and in fact yields an f_(s) equal tothe DVTR clock, and thus oscillator 931,932 is not needed for thisformat.

Step #10, f_(s) =N N_(T) f_(v) =(1375 total samples (bytes) per DVTRline) (900 total lines per frame) (59.94 fields per second)=74.17582418MHz.

Step 11, ##EQU13##

There are no remaining factors. Hence q=r=1 and f_(s) =74.17582418 MHzwhich is the same sampling frequency as the DVTR. Oscillators 930 and931 can be the same oscillator. N itself, 1375, is designated p.t=N_(DTL) =2200, s=f_(sD) /f_(v) =1237487, 2p=2750,n=2(N_(T))(p)=2(900)(1374)=2475000. The control circuitry can be builtfor the second source format by conforming the circuitry of FIGS. 6(a)and 6(b) per the above calculated values. FIGS. 14(a) and 14(b) showsuch circuitry connected as calculated above.

The record mode and playback mode circuits of FIGS. 6(a) and 6(b) can becombined using switches to connect plural components (such asoscillators 931, 932, 933 or 934) according to the desired mode.Furthermore, the circuits of FIGS. 12(a) and 12(b) through 14(a) and14(b) can be combined with switches to select a format to convert.Furthermore, the dividers can be programmable dividers to aid switchingbetween source formats. The above-mentioned switches and dividers can besubstituted with a program controlled processor wherein source formatdata are entered, parameters are calculated by the above embodimentsteps and clock and control signals are generated. It is also importantto note that the record/playback circuitry of FIGS. 4 and 5 can sharecommon components. For instance, it is preferred they share the sameDVTR and controller. It is also preferred they share the same memories.

TRANSFERRING A MOTION PICTURE FILM IMAGE TO DIGITAL MAGNETIC TAPE

The present invention is suitable for transferring motion pictures todigital magnetic tape for archival purposes without cropping the filmimage. Preferably, a non-interlaced, progressive scan luminance andchrominance output signal from a telecine, having a frame rate of 24frames per second, is digitized as 1920 active samples per line and 1290active lines per film frame. This provides a source format having thefollowing parameters:

a) N_(T) =1290 total lines per frame

b) N_(a) =1290 active lines per frame

c) f_(v) =24 fields per second

d) i=1 field per frame

Since motion picture film has a field rate of 1 field per frame, theframe rate of the film will be used in the following discussion.

The present invention can store this format on a DVTR using a conversiontechnique which is slightly different from the conversion techniquedescribed thus far. Generally, the conversion technique described aboveutilizes digital borrowing and carrying of active samples between sourceformat lines to form complete DVTR lines (with any dummy samples, ofcourse).

FIG. 7 shows that DVTR line 1 stores 1370 active samples 610 from line 1of the first exemplary source format are stored with 548 "borrowed"samples 611 from line 2. Two dummy samples 612 are added to these activesamples to complete DVTR line 1. In DVTR line 2, 822 "carried" activesamples 611 of source format line 2 are stored with 1096 samples 613 ofsource format line 3 (plus 2 dummy samples 614). DVTR line 3 stores 274"carried" samples 613 from source format line 3, all 1370 samples 615 ofsource format line 4, and 274 "borrowed" samples 616 from source formatline 5 (again, plus 2 dummy samples 617). DVTR line 4 stores 1096"carried" samples 615 from source format line 5 and 822 "borrowed"samples 618 from source format line 6 along with 2 dummy samples 619.DVTR line 5 holds 548 "borrowed" samples 618 from source format line 6and all 1370 samples 620 of source format line 7, plus 2 dummy samples621. DVTR line 6 shows the same arrangement of samples as stored in DVTRline 1, indicating that the pattern repeats.

For the conversion technique describe above, no borrows or carriesextend across field boundaries of the source format. That is, the numberof samples from a source format line selected to be stored on a DVTRline is such that one complete source format field is stored withoutborrowing or carrying any samples from an adjacent field. The conversiontechnique that follows borrows and carries lines between fields in muchthe same way as samples are borrowed and carried between lines of thesource format.

It turns out that 2 frames (fields) of the film are conveniently storedwithin 5 fields of the DVTR format. Since the field rate of the DVTR is2.5 times the frame rate of the film, to store 2 frames of film in 5files of the DVTR, (1290 active lines per film frame)/(2.5 DVTR fieldsper film frame)=516 active lines should be stored in each DVTR field. Aspreviously mentioned, a frame of the DVTR is stored at 1035 lines within2 fields, where 517 lines are stored in the first field and 518 linesare stored in the second field. The 516 film lines per DVTR field can beconveniently stored by including 1 dummy line with the first DVTR fieldand 2 dummy lines with the second DVTR field.

FIG. 15 shows a sequence of 516 lines from 2 consecutive film framesbeing stored in 5 consecutive DVTR fields. The first 516 lines of thefirst film frame plus 1 dummy line are stored in the 517 lines of thefirst DVTR field. The next 516 lines of the first film frame plus 2dummy lines are stored in the 518 lines of the second DVTR field. Theremaining 258 lines of the first film frame and the first 258 lines ofthe second film frame plus 1 dummy line are stored in the third DVTRfield. The next 516 lines of the second film frame plus 2 dummy linesare stored in the fourth DVTR field. The remaining 516 lines of thesecond film frame plus 1 dummy line are stored in the fifth DVTR field.

The dummy lines are used to carry film frame identification data forreconstructing the film image and to facilitate editing. The dummy linesassociated with a DVTR field in which 258 lines of two consecutive filmframes are stored will contain frame identification data for both filmframes. The frame identification data can be stored in the dummy linesin a highly redundant manner for an improved reconstruction error rate.

STRUCTURING THE CONVERTER PARAMETERS FOR CONVERTING A MOTION PICTUREFILM IMAGE TO A FORMAT FOR DIGITAL MAGNETIC RECORDING ACCORDING TO THEFIRST EMBODIMENT

Using the variables defined for the Sony HDD-1000 DVTR and for thetelecine source format, the following parameters are derived.

Step #1, N_(Da) field =N_(Da) /i_(D) =1035 active lines per frame/2fields per frame=517.5 active lines per field, N_(a) field =N_(a)/i=1290/1=1290 active lines per field.

Step #2, B=N_(DTL) N_(Da) field =(1920 active luminance samples (bytes)per line) (517.5 active lines per field)=993,600 active luminancesamples (bytes) per field.

Step #3, previously the number of active luminance samples per DVTR linewas specified as N_(c) =1920 active luminance samples (bytes) per activeline to conveniently store 2 film frames within 5 DVTR fields.

Step #4, N_(c) is an integer and n_(dcc) =0 dummy samples.

Step #5, N=N_(c) /0.85=(1920 active luminance samples (bytes) perline(/0.85=2258.82 total luminance samples (bytes) per active DVTR line.

Step #6, N=2259 total luminance samples (bytes) per active DVTR line,rounded to the nearest integer.

Step #7, N_(DTL) =2200=2×2×2×5×5×11.

Step #8, N=2259=3×3×251. No factors are common with the factors ofN_(DTL).

Step #9, increment and decrement N until the number of common factors ofN_(DTL) and N is greatest. We shall use N=2200 in this situation so that2 film frames are conveniently stored in 5 DVTR fields, as describedabove.

Step #10, f_(s) =N N_(T) f_(v) =(2200 total samples (bytes) per DVTRline) (1290 total lines per frame) (24 fields per second)(1 frame perfield)=68.112 MHz.

Step 11, ##EQU14##

The product of the remaining factors of N_(DTL) N_(DT) /i_(D) 3, 5 and5, equals 75 and is designated r. The product of the uncommon factors ofN and N_(T) 2, 3, 5 and 43, equals 172 and is designated q. N itself,2200, is designated p. The control circuitry can be built for theconverting film to digital tape by conforming the circuitry of FIGS.6(a) and 6(b) with the above calculated variables as illustrated inFIGS. 16(a) and 16(b).

STRUCTURING THE CONVERTER PARAMETERS FOR CONVERTING A MOTION PICTUREFILM IMAGE TO A FORMAT FOR DIGITAL MAGNETIC RECORDING ACCORDING TO THESECOND EMBODIMENT

Step #1, N_(Da) field =N_(Da) /i_(D) =1035 active lines per frame/2fields per frame=517.5 active lines per field, N_(a) field =N_(a)/i=1290 active lines per field/1 field per frame=1290 active lines perfield.

Step #1A, R=N_(Da) field /N_(a) field =517.5/1290=0.4. This value of Rshows that the number of active lines in a DVTR field is 0.4 the numberof lines produced by the telecine for a film frame. That is, 1 filmframe can be stored in 2.5 DVTR fields, or more conveniently, 2 filmframes can be stored in 5 DVTR fields.

Step #2, j/k=516/1290. j=516 lines is well matched to the 517-518 linesper field characteristic of the HDD-1000.

Step #3, N,=1920 active luminance samples (bytes) per line toconveniently store 2 film frames in 5 DVTR fields.

Step #4, N_(c) is an integer. Therefore, N_(c) =1920 active luminancesamples (bytes) per line and d=0 dummy samples per line.

Step #5, N=N_(c) /0.85=(1920 active luminance samples (bytes) perline(/0.85=2258.82 total luminance samples (bytes) per DVTR line.

Step #6, N=2259 total luminance samples (bytes) per DVTR line, roundedto the nearest integer.

Step #7, N_(DTL) =2200=2×2×2×5×5×11.

Step #8, N=2259=3×3×251. Again, 2259 factors very poorly and has nofactors in common with N_(DTL).

Step #9, increment and decrement N until the number of common factors ofN_(DTL) and N is greatest. Take the larger factors of 2200 to findnumbers close to 2033 having many of the same factors of 2200. We shalluse N=2200 so that 2 film frames are conveniently stored in 6 DVTRfields, as described above.

Step #10, f_(s) =N N_(T) f_(v) =(2200 total samples (bytes) per DVTRline) (1290 total lines per frame) (24 fields per second) (1 frame perfield)=63.112 MHz.

Step 11, ##EQU15##

The product of the remaining factors of N_(DTL) N_(DT) /i_(D), 3 5 and5, equals 75 and is designated r. The product of the uncommon factors ofN and N_(T) 2, 2 and 43, equals 172 and is designated q. N itself, 2200,is designated p. The control circuitry can be built for convertingmotion picture film to digital tape recording by conforming thecircuitry of FIGS. 6(a) and 6(b) with the above calculated variables asillustrated in FIGS. 16(a) and 16(b).

The above-described television source formats and motion picture film todigital tape recording are examples for teaching the present invention.These exemplary source formats are in no way preferred over each otheror any other source format. Using the principles taught by the abovedescription, conversions for recording and playing back of any sourceformat are possible.

THIRD EMBODIMENT FOR CONVERTING A MOTION PICTURE IMAGE TO A FORMAT FORDIGITAL MAGNETIC RECORDING

In the first and second embodiments for converting a motion picture filmimage to a format for digital magnetic recording, the number of activelines per frame was 1290. 1920 8-bit samples were stored in each line.While 8-bit resolution is suitable for most applications, still greaterluminance resolution can be obtained by using a standard DVTR. Inparticular, in accordance with this embodiment, nine bits are used foreach luminance sample.

To accomplish 9-bit luminance resolution, the number of active linesstored per frame of film is set to be 1200. Two frames of film are stillstored in 5 fields of DVTR. But rather than using 516 lines per tapefield for consecutive 8-bit samples, only 480 lines are used forconsecutive 8-bit samples. FIG. 17(a) illustrates this feature. In field1 of the DVTR is stored the first 480 lines of frame 1. In field 2 ofthe DVTR is stored the second 480 lines of frame 1 of the motionpicture. Since 480×2=960 and there are 1200 lines per motion pictureframe, there are 1200-960=240 lines left in frame 1. Those 240 lines arestored in the first 240 lines of tape field 3. The first 240 lines offrame 2 are stored in the next 240 lines of tape field 3. The next 480lines of frame 2 are stored in tape field 4. 480 lines of frame 2 areleft at this point and they are stored in tape field 5. Of course, asdiscussed in regard to FIG. 3, the DVTR stores 1920 samples per line ofluminance data and 1920 samples per line of chrominance data. Therefore,in actuality there are two sets of data in the DVTR like that shown inFIG. 17(a), one for luminance data, one for chrominance data.

But as discussed earlier, each tape field contains either 517 or 518lines, the number of lines per field alternating between 517 and 518.Thus, there are extra lines in each tape field not shown in FIG. 17(a).FIG. 17(b) show the extra lines. There are 37 or 38 extra lines in eachtape field. These additional lines are used to store the extra bitsrequired for 9-bit resolution. In this embodiment, only 37 lines perfield are used for the extra bits. That means that one line inalternative tape fields goes unused. Since the line is available only inalternative fields, its use add unnecessarily to the complexity of thesystem and the 37 lines provide sufficient storage for 9-bit resolution.Again, as discussed above, there are 37 extra lines for luminance dataand 37 extra lines for chrominance data.

To show that sufficient extra bits are available for 9-bit luminanceresolution, consider the two film frames of FIG. 17(a). There are atotal of 2400 active lines in those two frames (2×1200 active lines perframe). There are 1920×2400=4,608,000 samples in those two frames. Thus,to add a ninth bit to each sample, one needs 4,608,000 additional bits.

Referring to FIG. 17(b), there are five extra sets of 37 lines each or atotal of 185 lines. But there are 185 extra lines for luminance data and185 extra lines for chrominance data, for a total of 370 extra lines.Those 370 lines have 1920 8-bit bytes in them or a total of 710,400bytes of 8 bits each. That means there are 8×710,400=5,683,200 extrabits in those 5 tape fields. Thus, the 9th bits can be sequentiallystored in the extra lines, allowing 9 bits of resolution. Note thatluminance data is being stored in an area the DVTR interprets aschrominance data. This is necessary to have enough space to store allthe 9th bits. Only 9th bits for each luminance sample are stored. Allchrominance samples are 8 bits. However, the human eye is more sensitiveto brightness valves than to slight variations in color. Therefore,adding a ninth bit of luminance data is far more important than adding aninth bit of chrominance data.

Referring to FIG. 18, a block, diagram of a device in accordance withthis embodiment of the invention is shown. A motion picture scanner 802scans a motion picture and generates analog outputs representing theimage. One such device is called a telecine and several manufacturers,including, for example, Kodak, manufacture and sell such devices. Asshown in FIG. 18, chrominance and luminance data are provided by motionpicture scanner 802. However, the motion picture scanner 802 couldprovide R, G, B outputs as described in regard to FIG. 2. If so, amatrix 211, as shown as in FIG. 2, could be used to convert the R, G, Bdata to Y, P_(B) and P_(R) data. Similarly, a digital motion picturescanner 802 could be used.

Assuming an analog motion picture scanner 802, the chrominance andluminance data would be digitized in A/D converter 804. The chrominancevalues will be digitized to 8 bits. The luminance values will bedigitized to 9-bits. The digitized values will be passed to conversionmemory 806, where they will be stored and read at different rates toconvert the data to a format compatible with the DVTR, as has beendiscussed in detail earlier in this application. Of course, if P_(B) andP_(R) chrominance data are provided, conversion memory 806 willmultiplex them to a single chrominance data stream.

The 8-bit chrominance valves from conversion memory 806 are passed toDVTR 818 through selector 820 (discussed later) for recording aschrominance data as shown in FIG. 17(a).

The 9-bit luminance values pass to shift register 810. The leastsignificant bits of the 9-bit bytes are passed serially to bit store814. Bit store 814 collects all the 9th bits passed by shift register810. The output of bit store 814 is supplied to serial-to-parallelconverter 812, which form 8-bit bytes from the 9th bits. The output ofserial-to-parallel converter 812 is supplied to selector 816 andselector 820. Selector 816 selects either data from shift register 810or serial-to-parallel converter 812 for input to the DVTR 818 luminanceinput. Selector 820 selects either the 8-bit chrominance data fromconversion memory 806 or serial-to-parallel converter 812 for input tothe DVTR 818 chrominance input. Conversion memory 806, bit store 814,and selectors 816 and 820 are under the control of clock and controlcircuit 808, which controls the timing and operation of those elements.

In operation, during the first 480 lines of each tape field DVTR 818receives luminance and chrominance data from the conversion memory 806.That is, during this period, selectors 816 and 820 select chrominancedata from the conversion memory and the 8 most significant bits ofluminance data from the conversion memory, as supplied by shift register810. Also, during this period the 9th bits (least significant bits) ofthe luminance data are being collected and stored in bit store 814 byshift register 810. Starting with the 481st line and for 37 lines,selectors 816 and 820 select data from serial-to-parallel converter 812as chrominance and luminance inputs to DVTR 818. This process continuesuntil all the 9th bits are stored. Any remaining space in the tapefields can be used as dummy samples or dummy lines are previouslydescribed.

Referring now to FIG. 19A, the conversion from DVTR storage to motionpicture format output is described. In this embodiment, it is assumedthat the motion picture output will be displayed on a display 872 takingR, G, B inputs. Therefore, a matrix 870 is provided to give the R, G, Boutputs. Of course, the display could take chrominance and luminanceinputs directly and avoid the need for matrix 870. Further, display 872could accept digital inputs and avoid the need for D/A converter 886.

DVTR 818 outputs chrominance and luminance data streams of 8-bit bytes.Recall that the exemplary DVTR uses 2:1 interlacing. When odd fields arebeing output by the DVTR, demultiplexers 874 and 878 direct theluminance and chrominance data to odd field processor 880. When evenfields are being read by the DVTR, demultiplexers 874 and 878 direct thedata to even field processor 882. In the odd field processor 880 andeven field processor 882, the 9 bit luminance samples are reconstructed.The outputs of odd field processor 880 and even field processor 882 arefed to multiplexer 884, which selects data from one of the processors tosupply to conversion memory 885. When odd field data is being written toodd field processor 880, multiplexer 884 selects the data from evenfield processor 882 for provision to conversion memory 885 and viceversa.

More details of the odd field processor 880 may be found in FIG. 19B.Even field processor 882 is similar and will not be separated described.Chrominance and luminance data is received by the processor and passedto demultiplexers 887 and 888, respectively. During the first 480 linesof each field, demultiplexers 887 and 888 pass the chrominance andluminance data to chrominance field store 889 and luminance field store890, respectively. During the last 37 lines, the data is passed tospecial stores 891 and 892. The data stored in 891 and 892 then is the9th bits of luminance data and any dummy samples previously stored.After the field is completely read into the processor 880, an outputsequence begins. Note that during the output sequence of processor 880,processor 882 is receiving and storing data from the DVTR. Similarly,when a storing operation is occurring in processor 880, processor 882 isperforming an output sequence. The output sequence involves theformation of 9-bit luminance samples. Data is read from the chrominancestore 889 and luminance store 890 and passed to shift registers 893 and894, respectively. The 9th bit for that luminance sample is the readfrom special stores 891 or 892 and provided as the least significant bitto shift register 894. Shift register 894 then passes the 9 bitluminance data to its output.

The data from the outputs of odd field processor 880 and even fieldprocessor 882 are passed to multiplexer 884 (FIG. 19A), which selectsdata from one of the two processors to supply to its output. The outputof multiplexer 884 is passed to conversion memory 885 where the data isconverted to the output format, as has been previously described. Theoutputs of conversion memory 885, in a preferred embodiment, are Y_(D),P_(BD) and P_(RD) signals, which are then converted to analog signals inD/A converter 886. The analog signals are then converted to R,G,Bsignals in matrix 870 for display on display 872.

Consider the tape fields shown in FIG. 20. The one on the left is thechrominance data; the one on the right is the luminance data. Recallthat the first 480 lines of each field contain sequential 8-bit samples,either chrominance or luminance. In the last 37 lines are held extrabits necessary to give 9-bit resolution. Recall that for 9-bit luminanceresolution, 480×1920=921,600 extra bits are required. In the two sets of37 lines are 2×37×1920×8=1, 136, 640 bits. Thus, even after storing a9th bit for each luminance valve, there are 1, 136,640-921,600=215,040bits left. As discussed above, these bits could be used to storeadditional data, such as frame identification data. Moreover, the extrabits can be used to hold data giving 10-bit resolution for some of theluminance samples. Of course, since 215,040<921,600, 10th bits for eachluminance sample could not be stored. Rather, samples would be selectedso as to maximize the benefit of the 10th bits.

For example, as is well known in the art, human eyes as more sensitiveto the low frequency components of video signals than to high frequencycomponents. Therefore, a given amount of low frequency noise is oftenannoying to a viewer while the same amount of high frequency noise isalmost imperceptible. By providing 10-bit resolution for samplesrepresenting low frequency components, the picture quality, as perceivedby a viewer, can be significantly enhanced.

To implement such a partial 10-bit embodiment, it is preferable todigitize all the luminance components to 10 bits. Then, in the frequencydomain, take the samples through a low pass filter to separate out thelow frequencies and store them in 10 bits. The low frequency componentsare subtracted from the composite signal and the remaining samples havethe least significant bit truncated and are stored as 9-bit samples.

Since there are 921,600 samples and 215,040 extra bits,215,040/921,600=23% (approx.) of the luminance samples could be storedas 10 bits. For simplicity, in a preferred embodiment, 20% or 1/5 of theluminance samples are stored as 10-bits.

FIGS. 21-23 illustrate various digital filters that can be used with theinstant invention. FIG. 21 illustrates the simplest digital filter. Asshown, the 20% of the samples having the lowest horizontal frequencycomponents are chosen for 10-bit resolution.

FIG. 22 illustrates a digital filter that selects the lowest frequencyvertical components and lowest frequency horizontal components forstoring as 10-bits.

Finally, FIG. 23 shows a diagonal digital filter for choosing lowfrequency components. The diagonal filter is usually preferably since itselects more of the very low frequency vertical and horizontalcomponents than do the filters of FIGS. 21 and 22. These digital filtersand their implementation are well known in the art.

When the data is read for conversion back into film format, a look-uptable is employed to match the 9th bit (or 9th and 10th bits) with its(their) respective 8-bit sample. Note that the 9th bit (or 9th and 10thbits) is (are) a least significant bit(s). Therefore, if a lesssophisticated system is used for read-out, then the 9th bit (or 9th and10th bits) can be ignored. The system would use only the 8-bit samplessequentially stored in the first 480 lines of each tape field. By usingthis embodiment, 9-bit (or 10 bit) resolution is possible when needed,but the system is still compatible with 8-bit systems Similarly, if a9-bit conversion system is used, the 10th bits may be ignored.

In the 9-bit and 10-bit embodiments, 1200 scanning lines are used foreach frame of film. Note that in the 8-bit embodiment 1290 scanninglines were used per film frame. Thus, to provide 9-bit horizontalresolution, some vertical resolution is lost. Also, the 1200 lines is apreferred embodiment only. Other vertical resolutions may be chosen andfall within the scope of this invention.

I claim:
 1. An apparatus for converting a motion picture film imagesignal from a first film image signal format to a second signal format,the second signal format compatible with a digital tape recorder, thefirst film image signal format having a first frame rate and the secondsignal format having a first field rate, the apparatus comprising:amemory for storing first lines of data, the first lines of data storedin an arrangement representing both the first film image signal formatand the second signal format; first means, responsive to the first framerate, for generating a first synchronizing signal; second means,responsive to the first field rate, for generating a secondsynchronizing signal; and control means, coupled to the memory andresponsive to the first synchronizing signal and the secondsynchronizing signal, for storing the first lines of data in the memoryin synchronism with the first synchronizing signal and for reading thefirst lines of data from the memory in synchronism with the secondsynchronizing signal.
 2. The apparatus according to claim 1 furthercomprising a sampling circuit, responsive to the first means, forsampling the first film image signal format in synchronism with thefirst frame rate to produce the first lines of data stored in the memorywhen the first film image signal format is being converted to the secondsignal format.
 3. The apparatus according to claim 2 further comprisingdummy line generating means, coupled to the sampling circuit and thememory means and responsive to the first frame rate and the first fieldrate, for generating dummy lines of data for storage with the firstlines of data produced by the sampling circuit and stored in the memory.4. The apparatus according to claim 3, wherein the dummy lines of datainclude data related to frame identification of the first film imagesignal format.
 5. The apparatus according to claim 1 further comprisingdummy lines of data generating means, coupled to the memory means andresponsive to the first frame rate and the first field rate, forgenerating dummy lines of data for storage with the first lines of datastored in the memory.
 6. The apparatus according to claim 1, wherein theframe rate of the first film image signal format is 24 frames persecond, and the field rate of the second signal format is 60 fields persecond.
 7. An apparatus for converting a motion picture film image froma first signal format to a second signal format, the first signal formathaving a first frame comprising a first predetermined number of lines ofdata, and the second signal format having a first field comprising asecond predetermined number of lines of data, the apparatus comprising:amemory for storing lines of data; first means, responsive to the firstpredetermined number of lines of data of the first frame, for generatinga first timing signal; second means, responsive to the secondpredetermined number of lines of data of the first field, for generatinga second timing signal; determining means, coupled to the first meansand the second means, for determining a first predetermined number ofspare lines of data to be arranged with lines of data of the firstsignal format to form a first field; and control means, coupled to thememory and the determining means, for storing lines of data in thememory in response to the first timing signal and for reading lines ofdata from the memory in response to the second timing signal, the firstpredetermined number of spare lines of data being included with thelines of data read from the memory when the data is read to form a firstfield of the second signal format.
 8. The apparatus according to claim7, wherein the spare lines include frame identification data of thefirst signal format.
 9. A method of converting a motion picture filmimage signal from a first signal format to a second signal format, thesecond signal format compatible with a digital tape recorder, the firstsignal format having a first frame rate and the second signal formathaving a first field rate, the method comprising the steps of:generatinga first synchronizing signal in response to the first field rate;generating a second synchronizing signal in response to the first framerate; and storing first lines of data in a memory in synchronism withthe first synchronizing signal and reading the first lines of data fromthe memory in synchronism with the second synchronizing signal, thefirst lines of data stored in the memory in an arrangement representingboth the first signal format and the second signal format.
 10. Themethod according to claim 9 further comprising the step of storingsecond lines of data in the memory with the first lines of data insynchronism with the first synchronizing signal, and reading first linesof data and second lines of data from the memory in synchronism with thesecond synchronizing signal.
 11. The method according to claim 10wherein the second lines of data include frame identification data ofthe first signal format.
 12. An apparatus for converting a first signalformat to a first film image signal format, the first signal formatcompatible with a digital tape recorder, the first signal format havinga first field rate and the first film image signal format having a firstframe rate, the apparatus comprising:a memory for storing first lines ofdata, the first lines of data stored in an arrangement representing boththe first signal format and the first film image signal format; firstmeans, responsive to the first field rate, for generating a firstsynchronizing signal; second means, responsive to the first frame rate,for generating a second synchronizing signal; and control means, coupledto the memory and responsive to the first synchronizing signal and thesecond synchronizing signal, for storing the first lines of data in thememory in synchronism with the first synchronizing signal and forreading the first lines of data from the memory in synchronism with thesecond synchronizing signal.
 13. The apparatus according to claim 12wherein the first lines of data include dummy lines of data.
 14. Theapparatus according to claim 13, wherein the dummy lines of data includerelated to frame identification of the first film image signal format.15. The apparatus according to claim 22 further comprising formatassembly means, coupled to the memory means and responsive to the firstmeans and the second means, for assembling the first film image signalformat from the first lines of data read from the memory when the firstsignal format is being converted to the first film image signal format.16. The apparatus according to claim 12, wherein the field rate of thefirst signal format is 60 fields per second, and the frame rate of thefirst film image signal format is 24 frames per second.
 17. An apparatusfor converting a first signal format to a first film image signalformat, the first signal format having a first field comprising a firstpredetermined number of lines of data, and the first film image signalformat having a first frame comprising a second predetermined number oflines of data, the apparatus comprising:a memory for storing lines ofdata; first means, responsive to the first predetermined number of linesof data of the first field, for generating a first timing signal; secondmeans, responsive to the second predetermined number of lines of data ofthe first frame, for generating a second timing signal; and controlmeans, coupled to the memory and said first and second means forgenerating, for storing lines of data in the memory in response to thefirst timing signal and for reading lines of data from memory inresponse to the second timing signal.
 18. The apparatus according toclaim 17 wherein the lines of data include spare lines.
 19. Theapparatus according to claim 18, wherein the spare lines include fromidentification data of the first film image signal format.
 20. Theapparatus according to claim 17 further comprising film image formatassembly means, coupled to the memory and responsive to the secondtiming signal, for assembling the first film image signal format fromthe lines of data read from the memory when the first signal format isbeing converted to the first film image signal format.
 21. The apparatusaccording to claim 18 further comprising film image format assemblymeans, coupled to the memory and responsive to the second timing signal,for assembling the film image signal format from the lines of data readfrom the memory when the first signal format is being converted to thefirst film image signal format.
 22. The apparatus according to claim 21,wherein the first format reassembly means extracts frame identificationdata from the spare lines stored in the memory.
 23. A method ofconverting a first signal format to first film image signal format, thefirst signal format compatible with a digital tape recorder, the firstsignal format having a first field rate and the first film image signalformat having a first frame rate, the method comprising the stepsof:generating a first synchronizing signal in response to the firstfield rate; generating a second synchronizing signal in response to thefirst frame rate; and storing first lines of data in a memory insynchronism with the first synchronizing signal and reading the firstlines of data from the memory in synchronism with the secondsynchronizing signal.
 24. The method according to claim 23 furthercomprising the step of storing the second lines of data in the memorywith the first lines of data in synchronism with the first synchronizingsignal, and reading the first lines of data and the second lines of datafrom the memory in synchronism with the second synchronizing signal. 25.The method according to claim 24 wherein the second lines of datainclude frame identification data of the first film image signal format.26. An apparatus for converting an analog motion picture film imagesignal from a first film image signal format to a second signal format,the second signal format compatible with a digital tape recorder, thefirst film image signal format having a first frame rate and the secondsignal format having a first field rate, the apparatuscomprising:analog-to-digital converter means for converting said motionpicture film image signal to a luminance digital signal and achrominance digital signal, said chrominance digital signal comprisingsamples of Y bits each, said luminance digital signal comprising samplescomprising X bits each, where X>Y; memory means for storing saidluminance samples and chrominance samples, including means for storingsaid chrominance samples as consecutive Y bit samples and said luminancesamples as 1) consecutive Y bit samples and 2) additional samples forthe X-Y additional bits of each luminance sample; first means,responsive to the first frame rate, for generating a first synchronizingsignal; second means, responsive to the first field rate, for generatinga second synchronizing signal; and control means, coupled to the memorymeans and responsive to the first synchronizing signal and the secondsynchronizing signal, for storing the chrominance and luminance samplesin synchronism with said first synchronizing signal and for reading thechrominance and luminance samples in synchronism with said secondsynchronizing signal.
 27. An apparatus in accordance with claim 26wherein Y equals 8 and X equals
 9. 28. An apparatus in accordance withclaim 26 wherein Y equals 8 and X equals 9 or
 10. 29. An apparatus forconverting a motion picture film image signal from a first film imagesignal format to a second signal format, the second signal formatcompatible with a digital tape recorder, the first film image signalformat having a first frame rate and the second signal format having afirst field rate, said motion picture film image being defined bychrominance and luminance digital signals, the chrominance digitalsignal comprising consecutive Y bit samples, the luminance digitalsignal comprising consecutive X bit samples, where X>Y, the apparatuscomprising:memory means for storing said luminance samples andchrominance samples, including means for storing said chrominancesamples as consecutive Y bit samples and said luminance samples as 1)consecutive Y bit samples and 2) additional samples for the X-Yadditional bits of each luminance sample; first means, responsive to thefirst frame rate, for generating a first synchronizing signal; secondmeans, responsive to the first field rate, for generating a secondsynchronizing signal; and control means, coupled to the memory means andresponsive to the first synchronizing signal and the secondsynchronizing signal, for storing and chrominance and luminance samplesin synchronism with said first synchronizing signal and for reading thechrominance and luminance samples in synchronism with said secondsynchronizing signal.
 30. An apparatus in accordance with claim 29wherein Y equals and Y equals
 9. 31. An apparatus in accordance withclaim 29 wherein X equals 8 and Y equals 9 or
 10. 32. An apparatus forconverting an analog motion picture film image signal stored in a firstsignal format compatible with a digital tape recorder to a second signalformat comprising a motion picture signal film format, the first signalformat having a first field rate and the second signal format having afirst frame rate, said digital tape recorder supplying digitalchrominance signals comprising consecutive Y bit digital samples anddigital luminance signals comprising 1) consecutive Y bit digitalsamples and 2) additional samples having Y bits, each bit correspondingto one of said Y bit consecutive samples thereby providing X bitluminance samples, where X>Y, the apparatus comprising:memory means forstoring said luminance samples and chrominance samples, said memorymeans including means for reading said chrominance samples asconsecutive Y bit samples and said luminance samples as consecutive Xbit samples by reading said consecutive Y bit luminance samples andadding additional bits from said additional samples to give X bitluminance samples; first means, responsive to the first field rate, forgenerating a first synchronizing signal; second means, responsive to thefirst frame rate, for generating a second synchronizing signal; andcontrol means, coupled to the memory means and responsive to the firstsynchronizing signal and the second synchronizing signal, for storingand chrominance and luminance samples in synchronism with said firstsynchronizing signal and for reading the chrominance and luminancesamples in synchronism with said second synchronizing signal.
 33. Anapparatus in accordance with claim 32 wherein Y equals 8 and X equal 9.34. An apparatus in accordance with claim 32 wherein Y equals 8 and Xequals 9 or 10.